Design and Performance of Polymeric Ultra-thin Substrates for use as Embedded Capacitors: Comparison of Unfilled and Filled Systems with Ferroelectric Particles

2003 ◽  
Vol 783 ◽  
Author(s):  
John Andresakis ◽  
Takuya Yamamoto ◽  
Pranabes Pramanik ◽  
Nick Buinno

As CPUs increase in performance, the numbers of passive components on the surface of the boards are increasing dramatically. To reduce the number of components, as well as improve the electrical performance (i.e. reduce inductance), designers are increasingly embedding capacitive layers in the Printed Circuit Board (PCB).The majority of the products in use today utilize reinforced epoxy laminates. These products are relatively easy to handle and provide good electrical performance, but a need exists for even better performance than a fiberglass-reinforced product can produce.Other materials are being developed that are thinner (and thus increase capacitance and reduce inductance), but either have problems with dielectric breakdown strength, handling or only marginal improvements over the reinforced epoxy material. A need exists for an ultra-thin (less than 25 micron) material that not only provides improved electrical performance, but can be readily manufactured using standard PCB processing.We will discuss the design criteria we used for developing our family of products, as well as the results. The design of the conductor (copper foil) has been determined to be as critical as the properties of the dielectric (polymer). Examination of the effect of loading the polymer with High Dk ferroelectric particles will also be examined.The products have been through both internal and external testing and are compared to existing and developing capacitor materials. We will describe the electrical as well as the processing characteristics in detail, and how these types of products can greatly improve performance of high-speed systems

Author(s):  
Takuya Yamamoto ◽  
John Andresakis

As CPUs increase in performance, the number of passive components on the surface of the boards are increasing dramatically. To reduce the number of components, as well as improve the electrical performance (i.e. reduce inductance), designers are increasingly embedding capacitive layers in the PCB. The majority of the products in use today utilize reinforced epoxy laminates. These products are relatively easy to handle, but the thickness and Dk limit the effectiveness of the layer to perform as a capacitor. Other materials are being developed that are thinner (and thus increase capacitance), but either have problems with dielectric breakdown strength, handling or only marginal improvement over the existing material. This paper will describe new non-reinforced substrates for use as embedded capacitance layers that address these issues. The material selection process, substrate processing and electrical performance will be reviewed.


Author(s):  
Norman J. Armendariz ◽  
Carolyn McCormick

Abstract Via in pad PCB (Printed Circuit board) technology for passive components such as chip capacitors and resistors, provides the potential for improved signal routing density and reduced PCB area. Because of these improvements there is the potential for PCB cost reduction as well as gains in electrical performance through reduced impedance and inductance. However, not long after the implementation, double digit unit failures for solder joint electrical opens due to capacitor “tombstoning” began to occur. Failure modes included via fill material (solder mask) protrusion from the via as well as “out gassing” and related “tombstoning.” This failure analysis involved investigating a strong dependence on PCB supplier and, less obviously, manufacturing site. Other factors evaluated included via fill material, drill size, via fill thermal history and via fill amount or fill percent. The factor most implicated was incomplete cure of the via fill material. Previous thermal gravimetric analysis methods to determine level of polymerization or cure did not provide an ability to measure and demonstrate via fill cure level in small selected areas or its link to the failures. As a result, there was a metrology approach developed to establish this link and root-cause the failures in the field, which was based on microhardness techniques and noncontact via fill measuring metrologies.


Author(s):  
Vasudivan Sunappan ◽  
Chee Wai Lu ◽  
Lai Lai Wai ◽  
Wei Fan ◽  
Boon Keng Lok

A novel process has been developed to embed discrete (surface mountable) passive components like capacitors, resistors and inductors using printed circuit board fabrication technology. The process comprises of mounting passive components on top surface of a core PCB (printed circuit board) material using surface mount technology. The passive components mounting were designed in multiple clusters within the PCB. Dielectric sheets are sandwiched between top surface of core PCB and second PCB material for lamination process. A direct interconnection of the passive components to one or more integrated circuits (IC) is further accomplished by mounting the ICs on the bottom surface of the core material in an area directly under the passive components. The close proximity of the embedded passive components such as capacitors to an IC improved electrical performance by providing impedance reduction and resonance suppression at high frequency range. The reliability of solder joints was evaluatedd by temperature cycling test.


Author(s):  
O. Crépel ◽  
Y. Bouttement ◽  
P. Descamps ◽  
C. Goupil ◽  
P. Perdu ◽  
...  

Abstract We developed a system and a method to characterize the magnetic field induced by circuit board and electronic component, especially integrated inductor, with magnetic sensors. The different magnetic sensors are presented and several applications using this method are discussed. Particularly, in several semiconductor applications (e.g. Mobile phone), active dies are integrated with passive components. To minimize magnetic disturbance, arbitrary margin distances are used. We present a system to characterize precisely the magnetic emission to insure that the margin is sufficient and to reduce the size of the printed circuit board.


Author(s):  
P. Singh ◽  
G.T. Galyon ◽  
J. Obrzut ◽  
W.A. Alpaugh

Abstract A time delayed dielectric breakdown in printed circuit boards, operating at temperatures below the epoxy resin insulation thermo-electrical limits, is reported. The safe temperature-voltage operating regime was estimated and related to the glass-rubber transition (To) of printed circuit board dielectric. The TG was measured using DSC and compared with that determined from electrical conductivity of the laminate in the glassy and rubbery state. A failure model was developed and fitted to the experimental data matching a localized thermal degradation of the dielectric and time dependency. The model is based on localized heating of an insulation resistance defect that under certain voltage bias can exceed the TG, thus, initiating thermal degradation of the resin. The model agrees well with the experimental data and indicates that the failure rate and truncation time beyond which the probability of failure becomes insignificant, decreases with increasing glass-rubber transition temperature.


2021 ◽  
Author(s):  
Junyan Tang ◽  
Xianbo Yang ◽  
Jose A. Hejase ◽  
Mahesh Bohra ◽  
Yanyan Zhang ◽  
...  

2013 ◽  
Vol 333-335 ◽  
pp. 465-471
Author(s):  
Chuan Liu ◽  
Zhi Chao Huang ◽  
Peng Wu ◽  
Lei Chen ◽  
Wei Wang

Many applications in Power communication system have a demand of adjustable transmission time delay of high-speed signal. In sequential logic circuit, the control of transmission time delay of high-speed signal can effectively improve the accuracy of clock sampling, as a result, satisfy the constraints between clock signal and periodic data. A method of equivalent sampling based on printed circuit board (PCB) is provided in the article, it realizes equivalent sampling of the data by fixing a group of clock signal delay, thus, increase the accuracy of sampling.


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