Microhardness Testing on Via Fill Material for Via In Pad Technology

2003 ◽  
Author(s):  
Norman J. Armendariz ◽  
Carolyn McCormick
Keyword(s):  
Printed Circuit Board ◽  
Failure Modes ◽  
Strong Dependence ◽  
Circuit Board ◽  
Electrical Performance ◽  
Gravimetric Analysis ◽  
Passive Components ◽  
Root Cause ◽  
Fill Material ◽  
Signal Routing

Abstract Via in pad PCB (Printed Circuit board) technology for passive components such as chip capacitors and resistors, provides the potential for improved signal routing density and reduced PCB area. Because of these improvements there is the potential for PCB cost reduction as well as gains in electrical performance through reduced impedance and inductance. However, not long after the implementation, double digit unit failures for solder joint electrical opens due to capacitor “tombstoning” began to occur. Failure modes included via fill material (solder mask) protrusion from the via as well as “out gassing” and related “tombstoning.” This failure analysis involved investigating a strong dependence on PCB supplier and, less obviously, manufacturing site. Other factors evaluated included via fill material, drill size, via fill thermal history and via fill amount or fill percent. The factor most implicated was incomplete cure of the via fill material. Previous thermal gravimetric analysis methods to determine level of polymerization or cure did not provide an ability to measure and demonstrate via fill cure level in small selected areas or its link to the failures. As a result, there was a metrology approach developed to establish this link and root-cause the failures in the field, which was based on microhardness techniques and noncontact via fill measuring metrologies.

A Novel Discrete Passives Integration on Organic Substrate

2005 ◽  
Author(s):  
Vasudivan Sunappan ◽  
Chee Wai Lu ◽  
Lai Lai Wai ◽  
Wei Fan ◽  
Boon Keng Lok
Keyword(s):  
Integrated Circuits ◽  
Printed Circuit Board ◽  
Organic Substrate ◽  
Temperature Cycling ◽  
Circuit Board ◽  
Electrical Performance ◽  
Core Material ◽  
Bottom Surface ◽  
Passive Components ◽  
Printed Circuit

A novel process has been developed to embed discrete (surface mountable) passive components like capacitors, resistors and inductors using printed circuit board fabrication technology. The process comprises of mounting passive components on top surface of a core PCB (printed circuit board) material using surface mount technology. The passive components mounting were designed in multiple clusters within the PCB. Dielectric sheets are sandwiched between top surface of core PCB and second PCB material for lamination process. A direct interconnection of the passive components to one or more integrated circuits (IC) is further accomplished by mounting the ICs on the bottom surface of the core material in an area directly under the passive components. The close proximity of the embedded passive components such as capacitors to an IC improved electrical performance by providing impedance reduction and resonance suppression at high frequency range. The reliability of solder joints was evaluatedd by temperature cycling test.

scholarly journals Root Cause Analysis of a Printed Circuit Board (PCB) Failure in a Public Transport Communication System

2022 ◽  
Vol 12 (2) ◽  
pp. 640
Author(s):  
Cher-Ming Tan ◽  
Hsiao-Hi Chen ◽  
Jing-Ping Wu ◽  
Vivek Sangwan ◽  
Kun-Yen Tsai ◽  
...  
Keyword(s):  
Printed Circuit Board ◽  
Failure Modes ◽  
Essential Element ◽  
Circuit Board ◽  
Cause Analysis ◽  
Printed Circuit ◽  
Root Cause ◽  
Burn Out ◽  
Root Cause Identification

A printed circuit board (PCB) is an essential element for practical circuit applications and its failure can inflict large financial costs and even safety concerns, especially if the PCB failure occurs prematurely and unexpectedly. Understanding the failure modes and even the failure mechanisms of a PCB failure are not sufficient to ensure the same failure will not occur again in subsequent operations with different batches of PCBs. The identification of the root cause is crucial to prevent the reoccurrence of the same failure. In this work, a step-by-step approach from customer returned and inventory reproduced boards to the root cause identification is described for an actual industry case where the failure is a PCB burn-out. The failure mechanism is found to be a conductive anodic filament (CAF) even though the PCB is CAF-resistant. The root cause is due to PCB de-penalization. A reliability verification to assure the effectiveness of the corrective action according to the identified root cause is shown to complete the case study. This work shows that a CAF-resistant PCB does not necessarily guarantee no CAF and PCB processes can render its CAF resistance ineffective.

Design and Performance of Polymeric Ultra-thin Substrates for use as Embedded Capacitors: Comparison of Unfilled and Filled Systems with Ferroelectric Particles

2003 ◽  
Vol 783 ◽  
Author(s):  
John Andresakis ◽  
Takuya Yamamoto ◽  
Pranabes Pramanik ◽  
Nick Buinno
Keyword(s):  
High Speed ◽  
Printed Circuit Board ◽  
Dielectric Breakdown ◽  
Breakdown Strength ◽  
Circuit Board ◽  
Electrical Performance ◽  
Passive Components ◽  
Embedded Capacitors ◽  
Epoxy Material ◽  
And Performance

As CPUs increase in performance, the numbers of passive components on the surface of the boards are increasing dramatically. To reduce the number of components, as well as improve the electrical performance (i.e. reduce inductance), designers are increasingly embedding capacitive layers in the Printed Circuit Board (PCB).The majority of the products in use today utilize reinforced epoxy laminates. These products are relatively easy to handle and provide good electrical performance, but a need exists for even better performance than a fiberglass-reinforced product can produce.Other materials are being developed that are thinner (and thus increase capacitance and reduce inductance), but either have problems with dielectric breakdown strength, handling or only marginal improvements over the reinforced epoxy material. A need exists for an ultra-thin (less than 25 micron) material that not only provides improved electrical performance, but can be readily manufactured using standard PCB processing.We will discuss the design criteria we used for developing our family of products, as well as the results. The design of the conductor (copper foil) has been determined to be as critical as the properties of the dielectric (polymer). Examination of the effect of loading the polymer with High Dk ferroelectric particles will also be examined.The products have been through both internal and external testing and are compared to existing and developing capacitor materials. We will describe the electrical as well as the processing characteristics in detail, and how these types of products can greatly improve performance of high-speed systems

Root Cause Analysis of a Connector Time-Delayed Fracture

2015 ◽  
Author(s):  
Prabjit Singh ◽  
Ying Yu ◽  
Robert E. Davis
Keyword(s):  
Printed Circuit Board ◽  
Ceramic Substrate ◽  
Circuit Board ◽  
Delayed Fracture ◽  
Ceramic Substrates ◽  
Printed Circuit ◽  
Root Cause ◽  
Chip Carrier ◽  
Electrical Connections ◽  
Grain Boundary Grooves

Abstract A land-grid array connector, electrically connecting an array of plated contact pads on a ceramic substrate chip carrier to plated contact pads on a printed circuit board (PCB), failed in a year after assembly due to time-delayed fracture of multiple C-shaped spring connectors. The land-grid-array connectors analyzed had arrays of connectors consisting of gold on nickel plated Be-Cu C-shaped springs in compression that made electrical connections between the pads on the ceramic substrates and the PCBs. Metallography, fractography and surface analyses revealed the root cause of the C-spring connector fracture to be plating solutions trapped in deep grain boundary grooves etched into the C-spring connectors during the pre-plating cleaning operation. The stress necessary for the stress corrosion cracking mechanism was provided by the C-spring connectors, in the land-grid array, being compressed between the ceramic substrate and the printed circuit board.

Temperature and Humidity Dependent Reliability Analysis of RGB LED Chips

2006 ◽  
Author(s):  
Jun-Xian Fu ◽  
Shukri Souri ◽  
James S. Harris
Keyword(s):  
Reliability Analysis ◽  
Printed Circuit Board ◽  
Light Emitting Diode ◽  
Circuit Board ◽  
Light Emitting ◽  
Printed Circuit ◽  
Root Cause ◽  
Micro Cracks ◽  
Temperature And Humidity

Abstract Temperature and humidity dependent reliability analysis was performed based on a case study involving an indicator printed-circuit board with surface-mounted multiple-die red, green and blue light-emitting diode chips. Reported intermittent failures were investigated and the root cause was attributed to a non-optimized reflow process that resulted in micro-cracks and delaminations within the molding resin of the chips.

Magnetic Emission Mapping for Passive Integrated Components Characterisation

2003 ◽  
Author(s):  
O. Crépel ◽  
Y. Bouttement ◽  
P. Descamps ◽  
C. Goupil ◽  
P. Perdu ◽  
...  
Keyword(s):  
Magnetic Field ◽  
Mobile Phone ◽  
Printed Circuit Board ◽  
Magnetic Sensors ◽  
Circuit Board ◽  
Magnetic Disturbance ◽  
Passive Components ◽  
Printed Circuit ◽  
Integrated Inductor ◽  
The Magnetic Field

Abstract We developed a system and a method to characterize the magnetic field induced by circuit board and electronic component, especially integrated inductor, with magnetic sensors. The different magnetic sensors are presented and several applications using this method are discussed. Particularly, in several semiconductor applications (e.g. Mobile phone), active dies are integrated with passive components. To minimize magnetic disturbance, arbitrary margin distances are used. We present a system to characterize precisely the magnetic emission to insure that the margin is sufficient and to reduce the size of the printed circuit board.

Flexible Electronics Fabrication for Missile Wiring Interconnects

2012 ◽  
Vol 2012 (DPC) ◽  
pp. 001096-001114
Author(s):  
Michael R. Whitley ◽  
Tracy D. Hudson
Keyword(s):  
Unmanned Aerial Vehicles ◽  
Flexible Electronics ◽  
Printed Circuit Board ◽  
Circuit Board ◽  
Polyimide Films ◽  
Passive Components ◽  
Printed Circuit ◽  
Data Formats ◽  
Aerial Vehicles ◽  
Ink Jet

The increased usage of unmanned aerial vehicles has driven the desire for smaller and lighter missile bodies. The wiring harnesses required to connect the missile subsystems constitute a significant portion of the missile weight and cost. We have been exploring the development of flexible electronics substrates manufactured using ink jet technology on polyimide films. This technology has an advantage over traditional flex circuit manufacturing because in addition to creating traditional wiring patterns the ink jet technology enables the creation of passive components such as resistors and capacitors. The Dimatix DMP-2831 ink jet system uses individually controllable piezoelectric driven MEMS nozzles to precisely deposit nanoparticle inks. These inks are then annealed to form wiring patterns. We will present the process for converting traditional printed circuit board data formats to inkjet printable data, the process for depositing the ink, annealing and testing.

Analysis of 16 QFN Device I/O Pads for Solderability Failures

2015 ◽  
Vol 2015 (1) ◽  
pp. 000675-000684
Author(s):  
Rama Hegde ◽  
Anne Anderson ◽  
Sam Subramanian ◽  
Andrew Mawer ◽  
Ed Hall ◽  
...  
Keyword(s):  
Cross Section ◽  
Printed Circuit Board ◽  
Depth Profiling ◽  
Lessons Learned ◽  
Circuit Board ◽  
Physical Analysis ◽  
Lead Frame ◽  
Cross Sectional ◽  
Root Cause ◽  
Industry Standard

In-process failures were experienced during printed circuit board (PCB) SMT assembly of a 16 Quad Flat No Leads (QFN) device. The failures appeared to be solderability related with QFN unit I/O pads not soldering robustly and sometimes leading to QFN detachment following board mounting. When assembly did take place on affected QFN units, the resulting solder joint was observed to be weak. This paper reports on very systematic analyses of the QFN device I/O pads using optical inspections, AES surface, AES depth profiling, SEM/EDX, SIMS, FIB and TEM cross-sectional measurements to determine the root cause of the failure and the failure mechanism. The detached QFN units, suspect and good unsoldered units, passing and failing units obtained from customers were examined. The industry standard surface mount solderability testing was performed on good and suspect parts, and all were observed to pass as evidenced by >95% coverage of the I/O pads. Optical inspections and a wide variety of physical analysis of the pads on fresh parts showed no anomalies with only the expected Au over Pd over Ni found. AES analysis was performed including depth profiling to look for any issues in the NiPdAu over base Cu plating layers that could be contributing the solderability failures. The AES depth profiling indicated AuPd film on the Ni under layer for the I/O pads as expected. No unexpected elements or oxide layers were observed at any layer. Then, one failing and one passing units were compared by doing FIB cross-section, FIB planar section and TEM cross-section analysis. The cross-sectional analysis showed rough Ni surface for the failing units, while the Ni surface was relatively smooth for the passing unit. Further, finer Cu grains and Ni grains were observed on the passing units. Additionally, the lead frame fabrication process mapping showed rough Cu, Ni “texturing” and use of low electro chemical polishing (ECP) current on the bad units compared to that of the good units. All affected bad units were confirmed coming from a second source Cu supplier with the rough Cu. The weak and irregular NiSn IMC formation on the bad units caused IMC separation and possible spalling during board solder reflow primarily due to the rough base Cu and irregular grain sizes and resulting lower ECP lead frame plating current. A possible final factor was marginally low Pd thickness. In conclusion, the 16 QFN device solderability failure root cause summary and the lessons learned from a wide variety of analysis techniques will be discussed.

Process-Induced Thermal Effect on Packaging Yield of RF MEMS Switches

2002 ◽  
Author(s):  
Lei L. Mercado ◽  
Shun-Meen Kuo ◽  
Tien-Yu Tom Lee ◽  
Russ Lee
Keyword(s):  
Printed Circuit Board ◽  
Failure Modes ◽  
Rf Mems ◽  
Electrostatic Force ◽  
Circuit Board ◽  
Mems Switches ◽  
Rf Mems Switches ◽  
Significant Performance ◽  
And Performance ◽  
Lower Temperature

RF MEMS switches offer significant performance advantages in high frequency RF applications. The switches are actuated by electrostatic force when voltage was applied to the electrodes. Such devices provide high isolation when open and low contact resistance when closed. However, during the packaging process, there are various possible failure modes that may affect the switch yield and performance. The RF MEMS switches were first placed in a package and went through lid seal at 320°C. The assembled packages were then attached to a printed circuit board at 220°C. During the process, some switches failed due to electrical shorting. More interestingly, more failures were observed at the lower temperature of 220°C rather than 320°C. The failure mode was associated with the shorting bar and the cantilever design. Finite element simulations and simplified analytical solutions were used to understand the mechanics driving the behaviors. Simulation results have shown excellent agreement with experimental observations and measurements. Various solutions in package configurations were explored to overcome the hurdles in MEMS packaging and achieve better yield and performance.

An Experimental Assessment of Numerical Predictive Accuracy for Electronic Component Heat Transfer in Forced Convection—Part II: Results and Discussion

2003 ◽  
Vol 125 (1) ◽  
pp. 76-83 ◽  
Author(s):  
Peter J. Rodgers ◽  
Vale´rie C. Eveloy ◽  
Mark R. Davies
Keyword(s):  
Heat Transfer ◽  
Forced Convection ◽  
Printed Circuit Board ◽  
Predictive Accuracy ◽  
Numerical Models ◽  
Circuit Board ◽  
Junction Temperature ◽  
Electrical Performance ◽  
Test Cases ◽  
Computational Fluid Dynamics Cfd

Numerical predictive accuracy is assessed for component-printed circuit board (PCB) heat transfer in forced convection using a widely used computational fluid dynamics (CFD) software. In Part I of this paper, the benchmark test cases, experimental methods and numerical models were described. Component junction temperature prediction accuracy for the populated board case is typically within ±5°C or ±10%, which would not be sufficient for temperature predictions to be used as boundary conditions for subsequent reliability and electrical performance analyses. Neither the laminar or turbulent flow model resolve the complete flow field, suggesting the need for a turbulence model capable of modeling transition. The full complexity of component thermal interaction is shown not to be fully captured.

Sign in / Sign up

Export Citation Format

Share Document