Metal induced crystallization of SiGe at 370°C for monolithically integrated MEMS applications

2004 ◽  
Vol 808 ◽  
Author(s):  
Sherif Sedky ◽  
Kris Baert ◽  
Chris Van Hoof ◽  
Yi Wang ◽  
Omer Van Der Biest ◽  
...  
Keyword(s):  
Strain Gradient ◽  
Microelectromechanical Systems ◽  
Solid Phase ◽  
Active Material ◽  
Mean Stress ◽  
Germanium Content ◽  
Thermal Budget ◽  
Metal Induced Crystallization ◽  
Low Thermal Budget ◽  
Induced Crystallization

Over the last decade SiGe has been proposed as a structural material for low thermal budget microelectromechanical systems (MEMS) that can be post-processed on top of standard CMOS driving and controlling electronics [1-6]. There are several ways to decrease the deposition temperature of SiGe and at the same time preserve the desired physical properties for MEMS as low electrical resistivity, high quality factor, economical growth rate and low mean stress and strain gradient. The conventional approach to reduce the crystallization thermal budget is to increase the germanium content to 60%, or more, using conventional Low Pressure Chemical Vapor Deposition (LPCVD) [1-3]. In this case highly conductive polycrystalline films can be realized, but the strain gradient is relatively high. This can be eliminated by furnace annealing at 450°C [2], which might introduce damage to the underlying circuits such as in the case of Cu/low k CMOS. This problem can be alleviated using excimer pulsed laser annealing [7, 8], which has been attractive for low thermal budget applications such as thin film transistors (TFT) [9], solar cells fabricated on glass substrates [10] and for monolithic integration of MEMS devices on top of standard driving electronics using SiGe as an active material [8, 11]. Also the use of hydrogenated microcrystalline SiGe allows for a low thermal budget [12]. In addition, metal induced crystallization has recently been proposed to enhance the crystallization of silicon at temperatures as low as 500°C, and the realized devices had outstanding performance compared to those employing conventional solid-phase crystallization [13]. This technique enhances crystallization by two methods. First, it has been observed that depositing SiGe on top of a thin Al or Ni layer, has a polycrystalline micro-structure close to the metal/ SiGe interface [11]. Annealing this film for a long period (is determined by the annealing temperature), results in metal diffusion and a subsequent crystallization of the film. Finally, when the metal is diffused completely through out the film, it can be etched away. The main disadvantage of this approach is that the mean stress is highly compressive and this might affect the functionality of surface micromachined structures [13].

Directional Field Aided Lateral Crystallization of Amorphous Silicon Thin Films

2001 ◽  
Vol 664 ◽  
Author(s):  
Marek A. T. Izmajlowicz ◽  
Neil A. Morrison ◽  
Andrew J. Flewitt ◽  
William I. Milne
Keyword(s):  
Thin Films ◽  
Low Temperature ◽  
Electric Field ◽  
Amorphous Silicon ◽  
Solid Phase ◽  
Excimer Laser Annealing ◽  
Solid Phase Crystallization ◽  
Metal Induced Crystallization ◽  
Silicon Thin Films ◽  
Induced Crystallization

ABSTRACTFor application to active matrix liquid crystal displays (AMLCDs), a low temperature (< 600 °C) process for the production of polycrystalline silicon is required to permit the use of inexpensive glass substrates. This would allow the integration of drive electronics onto the display panel. Current low temperature processes include excimer laser annealing, which requires expensive equipment, and solid phase crystallization, which requires high temperatures. It is known that by adding small amounts of metals such as nickel to the amorphous silicon the solid phase crystallization temperature can be significantly reduced. The rate of this solid phase metal induced crystallization is increased in the presence of an electric field. Previous work on field aided crystallization has reported crystal growth that either proceeds towards the positive terminal or is independent of the direction of the electric field. In this work, extensive investigation has consistently revealed directional crystallization, from the positive to the negative terminal, of amorphous silicon thin films during heat treatment in the presence of an electric field. This is the first time that this phenomenon has been reported. Models have been proposed for metal induced crystallization with and without an applied electric field in which a reaction between Ni and Si to produce NiSi is the rate-limiting step. The crystallization rate is increased in the presence of an electric field through the drift of positive Ni ions.

Electrical characteristics of 8-/spl Aring/ EOT HfO/sub 2//TaN low thermal-budget n-channel FETs with solid-phase epitaxially regrown junctions

2006 ◽  
Vol 53 (7) ◽  
pp. 1657-1668 ◽  
Author(s):  
L.-A. Ragnarsson ◽  
S. Severi ◽  
L. Trojman ◽  
K.D. Johnson ◽  
D.P. Brunco ◽  
...  
Keyword(s):  
Solid Phase ◽  
Electrical Characteristics ◽  
Thermal Budget ◽  
Low Thermal Budget

Metal-catalyzed graphitization in Ni-C alloys and amorphous-C/Ni bilayers

2011 ◽  
Vol 1284 ◽  
Author(s):  
Katherine L. Saenger ◽  
Christian Lavoie ◽  
Roy Carruthers ◽  
Ageeth A. Bol ◽  
Timothy J. Mcardle ◽  
...  
Keyword(s):  
Chemical Vapor Deposition ◽  
Vapor Deposition ◽  
Solid Phase ◽  
Chemical Vapor ◽  
Graphitic Carbon ◽  
Metal Induced Crystallization ◽  
Annealing Conditions ◽  
Metal Catalyzed ◽  
Few Layer Graphene ◽  
Induced Crystallization

ABSTRACTMetal-catalyzed graphitization from vapor phase sources of carbon is now an established technique for producing few-layer graphene, a candidate material of interest for post-silicon electronics. Here we describe two alternative metal-catalyzed graphene formation processes utilizing solid phase sources of carbon. In the first, carbon is introduced as part of a cosputtered Ni-C alloy; in the second, carbon is introduced as one of the layers in an amorphous carbon (a-C)/Ni bilayer stack. We examine the quality and characteristics of the resulting graphene as a function of starting film thicknesses, Ni-C alloy composition or a-C deposition method (physical or chemical vapor deposition), and annealing conditions. We then discuss some of the competing processes playing a role in graphitic carbon formation and review recent evidence showing that the graphitic carbon in the a-C/Ni system initially forms by a metal-induced crystallization mechanism (analogous to what is seen with Al-induced crystallization of amorphous Si) rather than by the dissolution-upon-heating/precipitation-upon-cooling mechanism seen when graphene is grown by metal-catalyzed chemical vapor deposition methods.

Low Temperature Poly-Si Sputtering Deposition Through Metal-induced Crystallization and its Application

2006 ◽  
Vol 910 ◽  
Author(s):  
Hsiu-Wu Guo ◽  
Chen-Luen Shih ◽  
Joe Ketterl ◽  
Scott Dunham
Keyword(s):  
Solid Phase ◽  
Columnar Structure ◽  
Significant Loss ◽  
Nickel Silicide ◽  
Grain Structure ◽  
Cross Sectional ◽  
Sputtering Deposition ◽  
Metal Induced Crystallization ◽  
Transmission Electron ◽  
Induced Crystallization

AbstractGrowth of Si thin films via metal-induced crystallization (MIC) has been demonstrated by several research groups. This process lowers the crystallization temperature compared to standard solid phase crystallization (SPC). Ni is the metal that is most often adopted for this purpose. In this work, a 20-50nm Ni layer was deposited by DC magnetron sputtering onto a 500nm SiO2 layer grown on silicon wafers, followed by Si deposition at 500°C without breaking vacuum. X-ray diffraction (XRD) results and cross-sectional transmission electron microscopy (XTEM) confirmed the formation of poly-Si in a columnar structure with grain sizes in the 100-300nm range. XTEM and XPS show that nickel silicide was formed at the Si-Ni interface. We find that doping type and concentration do not have a significant impact on the grain structure. SIMS reveals no significant loss or redistribution in doping concentration during sputtering.

Ni-Silicided Deep Source/Drain Junctions Formed by Solid Phase Epitaxial Regrowth

2004 ◽  
Vol 810 ◽  
Author(s):  
Anne Lauwers ◽  
Richard Lindsay ◽  
Kirklen Henson ◽  
Simone Severi ◽  
Amal Akheyar ◽  
...  
Keyword(s):  
Contact Resistance ◽  
Solid Phase ◽  
Attractive Alternative ◽  
High Activation ◽  
Thermal Budget ◽  
Metal Gates ◽  
Epitaxial Regrowth ◽  
Deep Source ◽  
Low Thermal Budget

ABSTRACTMaking use of SPER (Solid Phase Epitaxial Regrowth) As and B deep source/drain junctions with high activation can be obtained at temperatures below 700°C. However, higher thermal budget is required to regrow and activate the dopants in the poly gates. Low junction leakage and low contact resistance can be obtained for Ni-silicided As and B SPER junctions making use of deep As and B implants. Because of the low thermal budget source/drain junctions obtained by SPER are an attractive alternative to conventional spike annealed junctions for technologies making use of metal gates.

Large ferroelectric polarization of TiN/Hf0.5Zr0.5O2/TiN capacitors due to stress-induced crystallization at low thermal budget

2017 ◽  
Vol 111 (24) ◽  
pp. 242901 ◽  
Author(s):  
Si Joon Kim ◽  
Dushyant Narayan ◽  
Jae-Gil Lee ◽  
Jaidah Mohan ◽  
Joy S. Lee ◽  
...  
Keyword(s):  
Ferroelectric Polarization ◽  
Thermal Budget ◽  
Low Thermal Budget ◽  
Stress Induced Crystallization ◽  
Induced Crystallization

Low thermal budget solid phase epitaxial growth of CaF2 on Si (111) substrates

1990 ◽  
Vol 19 (10) ◽  
pp. 1061-1064 ◽  
Author(s):  
R. Singh ◽  
R. P. S. Thakur ◽  
A. J. Nelson ◽  
S. C. Gebhard ◽  
A. B. Swartzlander
Keyword(s):  
Epitaxial Growth ◽  
Solid Phase ◽  
Thermal Budget ◽  
Low Thermal Budget

Solid Phase Epitaxy process integration on 50-nm PMOS devices: Effects of defects on chemical and electrical characteristics of ultra shallow junctions

2004 ◽  
Vol 810 ◽  
Author(s):  
R. El Farhane ◽  
C. Laviron ◽  
F. Cristiano ◽  
N. Cherkashin ◽  
P. Morin ◽  
...  
Keyword(s):  
Process Integration ◽  
Solid Phase ◽  
Cmos Process ◽  
Solid Phase Epitaxy ◽  
Electrical Characteristics ◽  
Use Of Self ◽  
Thermal Budget ◽  
Shallow Junctions ◽  
Ultra Shallow Junctions ◽  
Low Thermal Budget

ABSTRACTWe demonstrate in this paper the viability of an ultra-low thermal budget CMOS process enabling the formation of ultra shallow junctions with competitive transistor characteristics. In particular, we demonstrate in this work the influence of defects on chemical and electrical results. It is shown that the use of self-amorphizing implantation with BF2for Source/Drain, reduces the junction leakage by two decades.

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