Erbium-Silicided Source/Drain Junction Formation by Rapid Thermal Annealing Technique for Decananometer-Scale Schottky Barrier Metal-Oxide-Semiconductor Field- Effect Transistors

2004 ◽  
Vol 810 ◽  
Author(s):  
Moongyu Jang ◽  
Yarkyeon Kim ◽  
Jaeheon Shin ◽  
Kyoungwan Park ◽  
Seongjae Lee
Keyword(s):  
Schottky Barrier ◽  
Annealing Temperature ◽  
Field Effect Transistors ◽  
Growth Conditions ◽  
Silicon On Insulator ◽  
Oxide Semiconductor ◽  
Oxide Interface ◽  
Silicide Growth ◽  
Stable Growth ◽  
Optimum Annealing Temperature

ABSTRACTThe stable growth conditions of erbium-silicide on silicon-on-insulator (SOI) are investigated considering annealing temperature, SOI and sputtered erbium thickness. From the sheet resistance measurement, X-ray diffraction and Auger electron spectroscopy analysis, the optimum annealing temperature is determined as 500°C. Also, for the stable growth of erbium- silicide on SOI, the sputtered erbium thickness should be less than 1.5 times of SOI thickness. As the SOI thickness decreases below this critical thickness, erbium-rich region is formed at the erbium-silicide and buried-oxide interface. By applying the optimized erbium-silicide growth conditions, 50-nm-gate-length n-type SB-MOSFET is manufactured, which shows the possible usage of erbium-silicide as the source and drain material in the n-type Schottky barrier MOSFETs for decananometer regime applications.

Schottky-barrier height tuning using dopant segregation in Schottky-barrier MOSFETs on fully-depleted SOI

2006 ◽  
Vol 913 ◽  
Author(s):  
Joachim Knoch ◽  
Min Zhang ◽  
Qing-Tai Zhao ◽  
Siegfried Mantl
Keyword(s):  
Schottky Barrier ◽  
Barrier Height ◽  
Field Effect Transistors ◽  
Interface Layer ◽  
Silicon On Insulator ◽  
Oxide Semiconductor ◽  
Fully Depleted ◽  
Dopant Segregation ◽  
P Type ◽  
Silicon Interface

AbstractIn this paper we demonstrate the use of dopant segregation during silicidation for decreasing the effective potential barrier height in Schottky-barrier metal-oxide-semiconductor field-effect-transistors (SB-MOSFETs). N-type as well as p-type devices are fabricated with arsenic/boron implanted into the device's source and drain regions prior to silicidation. During full nickel silicidation a highly doped interface layer is created due to dopants segregating at the silicide-silicon interface. This doped layer leads to an increased tunneling probability through the Schottky barrier and hence leads to significantly improved device characteristics. In addition, we show with simulations that employing ultrathin body (UTB) silicon-on-insulator and ultrathin gate oxides allows to further improve the device characteristics.

Self-Assembly CoSi2-Nanostructures for Fabrication of Schottky Barrier MOSFETs on SOI

2001 ◽  
Vol 686 ◽  
Author(s):  
Patrick Kluth ◽  
Qing-Tai Zhao ◽  
Stephan Winnerl ◽  
Siegfried Mantl
Keyword(s):  
Schottky Barrier ◽  
Self Assembly ◽  
Strain Field ◽  
Field Effect Transistors ◽  
Silicon On Insulator ◽  
Oxide Semiconductor ◽  
Silicide Layer ◽  
20 Nm ◽  
Soi Substrates ◽  
Substrate Doping

AbstractA new self-assembly patterning method for generation of epitaxial CoSi2 nanostructures was used to fabricate 70 nm gate-length Schottky barrier metal oxide semiconductor field effect transistors (SBMOSFETs) on silicon-on-insulator (SOI) substrates. This technique involves only conventional optical lithography and standard silicon processing steps. It is based on anisotropic diffusion of Co/Si atoms in a strain field during rapid thermal processing. The strain field is generated along the edges of a mask consisting of 20 nm SiO2 and 300 nm Si3N4. Single-crystalline CoSi2 layers grown by molecular beam allotaxy (MBA) on thin SOI substrates were patterned using this technique. During rapid thermal oxinitridation (RTON) of the masked silicide structure, a well defined separation of the silicide layer forms along the edge of the mask. These highly uniform gaps define the channel region of the fabricated device. The separated silicide layers act as metal source and drain. During the RTON-step a 6 nm thin SiO2 is formed on top of the gap which is used as a gate oxide. The SBMOSFETs can be driven as both p-channel and n-channel devices without complementary substrate doping and show good I-V characteristics.

Self-Aligned Asymmetric Metal–Oxide–Semiconductor Field Effect Transistors Fabricated on Silicon-on-Insulator

2009 ◽  
Vol 48 (9) ◽  
pp. 091201
Author(s):  
Jong Pil Kim ◽  
Jae Young Song ◽  
Sang Wan Kim ◽  
Jae Hyun Park ◽  
Woo Young Choi ◽  
...  
Keyword(s):  
Metal Oxide ◽  
Field Effect ◽  
Field Effect Transistors ◽  
Metal Oxide Semiconductor ◽  
Silicon On Insulator ◽  
Oxide Semiconductor

scholarly journals A Programmable Impedance Tuner with a High Resolution Using a 0.18-um CMOS SOI Process for Improved Linearity

Electronics ◽  
2019 ◽  
Vol 9 (1) ◽  
pp. 7
Author(s):  
Younghwan Bae ◽  
Heesauk Jhon ◽  
Junghyun Kim
Keyword(s):  
Field Effect Transistors ◽  
Complementary Metal Oxide Semiconductor ◽  
Silicon On Insulator ◽  
Oxide Semiconductor ◽  
Impedance Variation ◽  
Measurement Results ◽  
Power Handling Capability ◽  
Impedance Tuners ◽  
Step Over ◽  
Load Pull

In this paper, a novel coupler/reflection-type programmable electronic impedance tuner combined with switches that were fabricated by a 0.18-um complementary metal–oxide–semiconductor (CMOS) silicon-on-insulator (SOI) process is proposed for replacement of the conventional mechanical tuner in power amplifier (PA) load-pull test. By employing the multi-stacked field-effect transistors (FETs) as a single-branch switch, the proposed tuner has the advantage of precise impedance variation with systematic and magnitude and phase adjustment. Additionally, it led to high standing wave ratio (SWR) coverage and a good impedance resolution with a high power handling capability. Furthermore, the double-branch based on multi-stacked FET was applied to switches for additional enhancement of the intermodulation distortion (IMD) performance through the mitigated drain-source voltage of the single-FET. Drawing upon the measurement results, we demonstrated that SWR changed from 2 to 6 sequentially with a 12–15° phase angle step over a mid/high-band range of a 1.5–2.1 GHz band for 3G/4G handset application. In addition, the PA load-pull measurement results obtained using the proposed tuners verified their practicality and competitive performance with mechanical tuners. Finally, the measured linearity using the double-branch switch demonstrated the good IMD3 performance of −78 dBc, and this result is noteworthy when compared with conventional electronic impedance tuners.

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