A 4-10bit, 0.4-1V Power Supply, Power Scalable Asynchronous SAR-ADC in 40nm-CMOS with Wide Supply Voltage Range SAR Controller

<span lang="EN-US">A sub-1V opamp based β-multiplier CMOS bandgap voltage reference (BGVR) with high power supply rejection ratio (PSRR) and low temperature coefficient (TC) is proposed in this paper. A current mode regulator scheme is inserted to isolate the supply voltage of the operational amplifier (opamp) and the supply voltage of the BGVR core from the supply voltage source in order to reduce ripple sensitivity and to achieve a high PSRR. The proposed circuit is designed and simulated in 0.18-μm standard CMOS technology. The proposed voltage reference delivers an output voltage of 634.6mV at 27°C. Tthe measurement temperature coefficient is 22,3ppm/°C over temperature range -40°C to 140°C, power supply rejection ratio is -93dB at 10kHz and -71dB at 1MHz and a line regulation of 104μV/V is achieved over supply voltage range 1.2V to 1.8V. The layout area of the proposed circuit is 0.0337mm<sup>2</sup>. The proposed sub-1V bandgap voltage reference can be used as an internal voltage reference in low power LDO regulators and switching regulators.</span>

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A 28 nm CMOS 10 bit 100 MS/s Asynchronous SAR ADC with Low-Power Switching Procedure and Timing-Protection Scheme

Electronics ◽

10.3390/electronics10222856 ◽

2021 ◽

Vol 10 (22) ◽

pp. 2856

Author(s):

Fang Tang ◽

Qiyun Ma ◽

Zhou Shu ◽

Yuanjin Zheng ◽

Amine Bermak

Keyword(s):

Dynamic Range ◽

Supply Voltage ◽

Sar Adc ◽

Cmos Process ◽

Power Switching ◽

Analog To Digital ◽

Protection Scheme ◽

Area Efficiency ◽

Asynchronous Sar ◽

28 Nm

This paper presents a 10 bit 100 MS/s asynchronous successive approximation register (SAR) analog-to-digital converter (ADC) without calibration for industrial control system (ICS) applications. Several techniques are adopted in the proposed switching procedure to achieve better linearity, power and area efficiency. A single-side-fixed technique is utilized to reduce the number of capacitors; a parallel split capacitor array in combination with a partially thermometer coded technique can minimize the switching energy, improve speed, and decrease differential non-linearity (DNL). In addition, a compact timing-protection scheme is proposed to ensure the stability of the asynchronous SAR ADC. The proposed ADC is fabricated in a 28 nm CMOS process with an active area of 0.026 mm2. At 100 MS/s, the ADC achieves a signal-to-noise-and-distortion ratio (SNDR) of 51.54 dB and a spurious free dynamic range (SFDR) of 55.12 dB with the Nyquist input. The measured DNL and integral non-linearity (INL) without calibration are +0.37/−0.44 and +0.48/−0.63 LSB, respectively. The power consumption is 1.1 mW with a supply voltage of 0.9 V, leading to a figure of merit (FoM) of 35.6 fJ/conversion-step.

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Improvement of Multilevel DC/DC Converter for E-Mobility Charging Station

Electronics ◽

10.3390/electronics9122037 ◽

2020 ◽

Vol 9 (12) ◽

pp. 2037 ◽

Cited By ~ 1

Author(s):

Jung-Hwan Lee ◽

Sung-Jun Park ◽

Sang-Kil Lim

Keyword(s):

Power Supply ◽

Supply Voltage ◽

Input Power ◽

Buck Converter ◽

Operating Conditions ◽

Multilevel Converter ◽

Power Supply Voltage ◽

Personal Mobility ◽

Voltage Range ◽

Charging System

Considerable efforts are being made to reduce CO2 emissions and thereby solve the problems of environmental pollution and global warming. Technologies for environmentally friendly transportation are being developed using batteries. In particular, with the increase in urbanization and one-person households, e-mobility products are drawing increasing attention as short-distance transportation devices. Among these vehicles, personal mobility devices (PMDs) are receiving attention as new transportation devices that are simple to operate. This paper proposes a new multilevel charging system that is advantageous in responding to the charging voltage specifications of various mobile devices with a single charging system while ensuring a low charging current ripple. The proposed diode-parallel multilevel converter consists of an independent Buck converter in series. The switch of the buck converter is configured at the negative terminal of the input power source so that the gate amplifier voltage is used as the power supply voltage; it can therefore be simply configured without a separate gate amplifier power supply. In addition, it is improved so as to have a wider charging voltage range in a low output voltage region and a better efficiency than the existing diode series multilevel converter. To verify the feasibility of the proposed system, simulations were performed using the software PowerSIM(PSIM), and, in order to verify the validity, a prototype charging system was fabricated to compare and analyze losses according to operating conditions.

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A 10-bit 10-MS/s single-ended asynchronous SAR ADC with CDAC boosting common-mode voltage and controlling input voltage range

IEICE Electronics Express ◽

10.1587/elex.16.20190597 ◽

2019 ◽

Vol 16 (22) ◽

pp. 20190597-20190597

Author(s):

Jisu Son ◽

Young-Chan Jang

Keyword(s):

Input Voltage ◽

Sar Adc ◽

Common Mode ◽

Voltage Range ◽

Common Mode Voltage ◽

Asynchronous Sar

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Wide-Supply-Voltage-Range CMOS Bandgap Reference for In Vivo Wireless Power Telemetry

Energies ◽

10.3390/en13112986 ◽

2020 ◽

Vol 13 (11) ◽

pp. 2986 ◽

Cited By ~ 4

Author(s):

Ruhaifi Bin Abdullah Zawawi ◽

Wajahat H. Abbasi ◽

Seung-Hwan Kim ◽

Hojong Choi ◽

Jungsuk Kim

Keyword(s):

Power Supply ◽

Supply Voltage ◽

Channel Length ◽

Power Supply Voltage ◽

Voltage Range ◽

Power Supply Rejection Ratio ◽

Wide Range ◽

Reference Circuit ◽

Inherent Problem

The robustness of the reference circuit in a wide range of supply voltages is crucial in implanted devices. Conventional reference circuits have demonstrated a weak performance over wide supply ranges. Channel-length modulation in the transistors causes the circuit to be sensitive to power supply variation. To solve this inherent problem, this paper proposes a new output-voltage-line-regulation controller circuit. When a variation occurs in the power supply, the controller promptly responds to the supply deviation and removes unwanted current in the output path of the reference circuit. The proposed circuit was implemented in a 0.35-μm SK Hynix CMOS standard process. The experimental results demonstrated that the proposed reference circuit could generate a reference voltage of 0.895 V under a power supply voltage of 3.3 V, line regulation of 1.85 mV/V in the supply range of 2.3 to 5 V, maximum power supply rejection ratio (PSRR) of −54 dB, and temperature coefficient of 11.9 ppm/°C in the temperature range of 25 to 100 °C.

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