scholarly journals Comparative analysis of methods for constructing analog-to-digital converters

2020 ◽  
pp. 38-49
Author(s):  
Aleksander Ulyashin ◽  
◽  
Aleksander Velichko ◽  
Keyword(s):  
Comparative Analysis ◽  
High Speed ◽  
Frequency Conversion ◽  
Dynamic Range ◽  
Simultaneous Detection ◽  
Integrated Design ◽  
Analog To Digital Converters ◽  
Measurement Technology ◽  
Main Task ◽  
Analog To Digital

This paper is devoted to the comparative analysis of modern integrated analog-to-digital converters (ADCs). At the moment, a number of foreign companies, such as Analog Devices, Texas Instruments and Microchip, produce ADCs in integrated design. Each manufacturer uses its own method of implementing the device. The main task of such devices is to convert voltage to binary code. ADCs are used wherever it is necessary to receive an analog signal and process it in digital form. Examples include applications such as communications and telecommunications, various radio systems, and measurement technology. Very important characteristics of such equipment are dynamic range, ease of implementation and speed. The means of analog-to-digital conversion are constantly being improved, which leads to an increase in the speed of the converters and the frequency band of the converted signals, an increase in the dynamic range, sensitivity and accuracy of the ADC. Significant interest in high-speed ADCs with a large dynamic range is explained by the fact that in the vast majority of telecommunications and radio engineering systems, direct signal conversion schemes without intermediate frequency conversion are increasingly used. Broadband applications have also been developed. The main requirement in these applications is the high sensitivity and wide dynamic range of the transducer for simultaneous detection of strong and weak signals. In this paper, a comparative analysis of the main types of analog-to-digital converters offered on the market is carried out in order to identify the most optimal construction method for using it in modern equipment.

Comparative analysis of analog parameters signal multi-pliers by differential transistor pairs

2021 ◽  
pp. 21-41
Author(s):  
Aleksander Ulyashin ◽  
◽  
Aleksander Velichko ◽  
Keyword(s):  
Comparative Analysis ◽  
Dynamic Range ◽  
Integrated Design ◽  
Internal Noise ◽  
Main Task ◽  
External Interference ◽  
Foreign Companies ◽  
Upper Limit ◽  
Radio Equipment ◽  
Overload Capacity

This paper is devoted to the comparative analysis of modern integral variables. Today, a number of foreign companies, such as Texas Instruments and Analog Devices, produce analog signal multipliers (APS) in integrated design. Russian industry produces chips of the 525PS and 174HA series. Each manufacturer uses its own method of implementing the device. The main task of such devices is to calculate the current voltage, phase, exponential and transcendental functions. Wide applicability of APS in integrated design was found in devices for analog processing and conversion of signals of communication and radio equipment, in devices for automatic control of onboard and ground radio equipment. A very important characteristic of such equipment is the dynamic range. The dynamic range of the receiver is the range of input signal amplitudes that provide the required quality of reproduction of the received message. The lower limit of the dynamic range is determined by the level of internal noise or external interference in the device, and the upper limit is determined by the device's overload capacity. In this regard, manufacturers of multipliers are faced with the task of maximizing the voltage that can be applied to its inputs. The difficulty is that the upper limit of the dynamic range is set by non-linear distortions. The non-linearity of the multiplier is a component of the multiplication error and characterizes the limiting capabilities of the APS inputs. In this paper, a comparative analysis of the main types of integral multipliers offered on the market is carried out in order to identify the best construction method for achieving the value of the dynamic range of the multiplier in 90 dB with high multiplication accuracy, which will allow using such a multiplier in modern radio equipment.

scholarly journals An Improved All-Digital Background Calibration Technique for Channel Mismatches in High Speed Time-Interleaved Analog-to-Digital Converters

Electronics ◽  
2020 ◽  
Vol 9 (1) ◽  
pp. 73
Author(s):  
Van-Thanh Ta ◽  
Van-Phuc Hoang ◽  
Van-Phu Pham ◽  
Cong-Kha Pham
Keyword(s):  
Communication Systems ◽  
High Speed ◽  
Dynamic Range ◽  
Analog To Digital Converters ◽  
Background Calibration ◽  
Calibration Technique ◽  
Analog To Digital ◽  
Digital Background Calibration ◽  
Field Programmable ◽  
Time Interleaved

The time-interleaved analog-to-digital converters (TIADCs), performance is seriously affected by channel mismatches, especially for the applications in the next-generation communication systems. This work presents an improved all-digital background calibration technique for TIADCs by combining the Hadamard transform for calibrating gain and timing mismatches and averaging for offset mismatch cancellation. The numerical simulation results show that the proposed calibration technique completely suppresses the spurious images due to the channel mismatches at the output spectrum, which increases the spurious-free dynamic range (SFDR) and signal-to-noise and distortion ratio (SNDR) by 74 dB and 43.7 dB, respectively. Furthermore, the hardware co-simulation on the field programmable gate array (FPGA) platform is performed to confirm the effectiveness of the proposed calibration technique. The simulation and experimental results clarify the improvement of the proposed calibration technique in the TIADC’s performance.

A Bandwidth Mismatch Optimization Technique in Time-Interleaved Analog-to-Digital Converters

2019 ◽  
Vol 28 (06) ◽  
pp. 1950090
Author(s):  
Jian Luo ◽  
Jing Li ◽  
Shuangyi Wu ◽  
Ning Ning ◽  
Yang Liu
Keyword(s):  
Simulated Annealing Algorithm ◽  
Dynamic Range ◽  
Optimization Technique ◽  
Analog To Digital Converters ◽  
Analog To Digital ◽  
Limited Bandwidth ◽  
Behavior Simulation ◽  
Calibration Methods ◽  
Time Interleaved ◽  
Sampling Sequences

In time-interleaved (TI) analog-to-digital converters (ADCs), bandwidth mismatches, caused by the limited bandwidth of input signal traces and sample circuits, seriously deteriorate the spurious-free dynamic range (SFDR) of the system. This paper analyzes the influence of bandwidth mismatch errors under different sampling sequences. Eventually, based on a randomization technique and the simulated annealing algorithm (SAA), a bandwidth mismatch optimization technique is presented that can work well with other bandwidth mismatch calibration methods. The behavior simulation results indicate that an improvement of 7[Formula: see text]dB in the SFDR can be achieved with this technique in a 16-channel TI-ADC after timing and gain calibration.

scholarly journals A Novel Highly Linear Voltage-To-Time Converter (VTC) Circuit for Time-Based Analog-To-Digital Converters (ADC) Using Body Biasing

Electronics ◽  
2020 ◽  
Vol 9 (12) ◽  
pp. 2033
Author(s):  
Ahmed Elgreatly ◽  
Ahmed Dessouki ◽  
Hassan Mostafa ◽  
Rania Abdalla ◽  
El-sayed El-Rabaie
Keyword(s):  
Power Consumption ◽  
Software Defined Radio ◽  
Dynamic Range ◽  
Supply Voltage ◽  
Cmos Technology ◽  
The Body ◽  
Analog To Digital Converters ◽  
Clock Frequency ◽  
Analog To Digital ◽  
Operation Speed

Time-based analog-to-digital converter is considered a crucial part in the design of software-defined radio receivers for its higher performance than other analog-to-digital converters in terms of operation speed, input dynamic range and power consumption. In this paper, two novel voltage-to-time converters are proposed at which the input voltage signal is connected to the body terminal of the starving transistor rather than its gate terminal. These novel converters exhibit better linearity, which is analytically proven in this paper. The maximum linearity error is reduced to 0.4%. In addition, the input dynamic range of these converters is increased to 800 mV for a supply voltage of 1.2 V by using industrial hardware-calibrated TSMC 65 nm CMOS technology. These novel designs consist of only a single inverter stage, which results in reducing the layout area and the power consumption. The overall power consumption is 18 μW for the first proposed circuit and 15 μW for the second proposed circuit. The novel converter circuits have a resolution of 5 bits and operate at a maximum clock frequency of 500 MHz.

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