Implementation of Low Voltage MOSFET and Power LDMOS on InGaAs

Abstract In this paper, a new low voltage MOSFET (LV MOSFET) and high voltage dual-gate MOSFET (HV DG MOSFET) have been proposed with concept of integration based on trench technology on InGaAs material. Junction isolation technique is used for the implementation of a low voltage MOSFET and a high power dual gate MOSFET in same InGaAs epitaxial layer side by side. The HV DG MOSFET consists of dual gate that are placed in drift region under the oxide-filled trenches. The proposed structure minimize on-resistance (R on ) along with increased breakdown voltage (V br ) due to enhanced RESURF effect, the creation of dual channels, and due to folding technique of drift region in vertical direction. In the HV DG MOSFET, the drain current (I D ) increases leading to enhanced transconductance (gm) by simultaneous conduction of channels with improved maximum oscillation frequency (f max ) and cut-off frequency (f t ). On the other side, the low voltage MOSFET consists of a gate placed in a centre of the structure within an oxide trench to create two n-channels in the p-base. The two channels are conducting in parallel and give substantial enhancement in peak g m , I D , f max and f t with more control over the short channel parameters. The design and performance analysis of low voltage MOSFET (LV MOSFET) and high voltage dual-gate MOSFET (HV DG MOSFET) are carried out on 2-D ATLAS device simulator.

Download Full-text

High Voltage and Fast Switching Reverse Recovery Characteristics of 4H-SiC PiN Diode

Materials Science Forum ◽

10.4028/www.scientific.net/msf.778-780.841 ◽

2014 ◽

Vol 778-780 ◽

pp. 841-844 ◽

Cited By ~ 1

Author(s):

Koji Nakayama ◽

Shuji Ogata ◽

Toshihiko Hayashi ◽

Tetsuro Hemmi ◽

Atsushi Tanaka ◽

...

Keyword(s):

High Voltage ◽

Recovery Time ◽

Carrier Lifetime ◽

Low Voltage ◽

Reduction Rate ◽

Drift Region ◽

Pin Diode ◽

Fully Depleted ◽

Fast Switching ◽

Reverse Recovery Time

The reverse recovery characteristics of a 4H-SiC PiN diode under higher voltage and faster switching are investigated. In a high-voltage 4H-SiC PiN diode, owing to an increased thickness, the drift region does not become fully depleted at a relatively low voltage Furthermore, an electron–hole recombination must be taken into account when the carrier lifetime is equal to or shorter than the reverse recovery time. High voltage and fast switching are therefore needed for accurate analysis of the reverse recovery characteristics. The current reduction rate increases up to 2 kA/μs because of low stray inductance. The maximum reverse voltage during the reverse recovery time reaches 8 kV, at which point the drift layer is fully depleted. The carrier lifetime at the high level injection is 0.086 μs at room temperature and reaches 0.53 μs at 250 °C.

Download Full-text

Towards High-Voltage MOSFETs in Ultrathin FDSOI

International Journal of High Speed Electronics and Systems ◽

10.1142/s012915641640005x ◽

2016 ◽

Vol 25 (01n02) ◽

pp. 1640005 ◽

Cited By ~ 3

Author(s):

Antoine Litty ◽

Sylvie Ortolland ◽

Dominique Golanski ◽

Christian Dutto ◽

Alexandres Dartigues ◽

...

Keyword(s):

High Voltage ◽

Low Voltage ◽

Ground Plane ◽

Silicon Film ◽

Silicon On Insulator ◽

Drift Region ◽

Back Gate ◽

Fully Depleted ◽

Buried Oxide ◽

Core Technology

High-Voltage MOSFETs are essential devices for complementing and extending the domains of application of any core technology including low-power, low-voltage CMOS. In this paper, we propose and describe advanced Extended-Drain MOSFETs, designed, processed and characterized in ultrathin body and buried oxide Fully Depleted Silicon on Insulator technology (UTBB-FDSOI). These transistors have been implemented in two technology nodes (28 nm and 14 nm) with different silicon film and buried oxide thicknesses (TSi < 10nm and TBOX ≤ 25nm). Our innovative concept of Dual Ground Plane (DGP) provides RESURF-like effect (reduced surface field) and offers additional flexibility for HVMOS integration directly in the ultrathin film of the FDSOI wafer. In this configuration, the primary back-gate controls the threshold voltage (VTH) to ensure performance and low leakage current. The second back-gate, located underneath the drift region, acts as a field plate enabling the improvement of the ON resistance (RON) and breakdown voltage (BV). The trade-off RON.S versus BV is investigated as a function of doping level, length and thickness of the drift region. We report promising results and discuss further developments for successful integration of high-voltage MOSFETs in ultrathin CMOS FDSOI technology.

Download Full-text

A Compact Short-Channel Analytical Drain Current Model of Asymmetric Dual-Gate TMD FET in Subthreshold Region Including Fringing Field Effects

IEEE Access ◽

10.1109/access.2020.3038421 ◽

2020 ◽

Vol 8 ◽

pp. 207982-207990

Author(s):

Niraj Kumar Singh ◽

Monika Kumari ◽

Manodipan Sahoo

Keyword(s):

Current Model ◽

Drain Current ◽

Short Channel ◽

Subthreshold Region ◽

Field Effects ◽

Fringing Field ◽

Dual Gate

Download Full-text

Layout Strengthening the ESD Performance for High-Voltage N-Channel Lateral Diffused MOSFETs

Electronics ◽

10.3390/electronics9050718 ◽

2020 ◽

Vol 9 (5) ◽

pp. 718

Author(s):

Sheng-Kai Fan ◽

Shen-Li Chen ◽

Po-Lin Lin ◽

Hung-Wei Chen

Keyword(s):

Schottky Diode ◽

High Voltage ◽

Low Voltage ◽

Channel Width ◽

Drift Region ◽

Operating Voltage ◽

Equivalent Series Resistance ◽

Drain Side ◽

Region Length ◽

Latch Up

An electrostatic discharge (ESD) event can negatively affect the reliability of integrated circuits. Therefore, improving on ESD immunity in high-voltage (HV) n-channel (n) lateral diffused metal–oxide–semiconductor field-effect transistor (HV nLDMOS) components through drain-side layout engineering was studied. This involved adjusting the operating voltage, improving the non-uniform turned-on phenomenon, and examining the effects of embedded-device structures on ESD. All proposed architectures for improving ESD immunity in this work were measured and evaluated using a transmission-line pulse system. The corresponding trigger voltage (Vt1), holding voltage (Vh) and secondary breakdown current (It2) results of the tested devices were obtained. This paper first addresses the drift-region length modulation to design different operating voltages, which decreased as the drift region length and shallow trench isolation (STI) length shrunk. When an HV nLDMOS device decreased to the shortest drift region length, the Vt1 and Vh values were closest to 21.85, and 9.27 V, respectively. The It2 value of a low-voltage operated device could be increased to a maximum value of 3.25 A. For the channel width modulation, increasing the layout finger number of an HV LDMOS device did not really help the ESD immunity that because it may suffer the problem of non-uniform turned-on phenomenon. Therefore, adjusting the optimized channel width was the best one method of improvement. Furthermore, to improve the low ESD reliability problem of nLDMOS devices, two structures were used to improve the ESD capability. The first was a drain side—embedded silicon-controlled rectifier (SCR). Here, the SCR PNP-arranged type in the drain side had the best ESD capability because the SCR path was short and had been prior to triggering; however, it also has a latch-up risk and low Vh characteristic. By removing the entire heavily doped drain-side N+ region, the equivalent series resistance in the drain region was increased, so that the It2 performance could be increased from 2.29 A to 3.98 A in the structure of a fully embedded drain-side Schottky diode. This component still has sufficiently high Vh behaviour. Therefore, embedding a full Schottky-diode into an HV nLDMOS in the drain side was the best method and was efficient for improving the ESD/Latch-up abilities of the device. The figure of merit (FOM) of ESD, Latch-up, and cell area considerations improved to approximately 80.86%.

Download Full-text

VJFET Based All-SiC Normally-Off Cascode Switch for High Temperature Power Handling Applications

Materials Science Forum ◽

10.4028/www.scientific.net/msf.615-617.711 ◽

2009 ◽

Vol 615-617 ◽

pp. 711-714 ◽

Cited By ~ 10

Author(s):

Victor Veliadis ◽

Harold Hearne ◽

Ty McNutt ◽

Megan Snook ◽

Paul Potyraj ◽

...

Keyword(s):

High Voltage ◽

Threshold Voltage ◽

Electron Mobility ◽

Low Voltage ◽

Field Effect Transistors ◽

Drain Current ◽

Current Gain ◽

Power Switching ◽

Thermally Induced ◽

C Value

High-voltage vertical-junction-field-effect-transistors (VJFETs) are typically designed normally-on to ensure low-resistance voltage-control operation at high current-gain. To exploit the high-voltage/temperature capabilities of VJFETs in a normally-off voltage-controlled switch, high-voltage normally-on and low-voltage normally-off VJFETs were connected in the cascode configuration. The cascode gate’s threshold voltage decreases from 2.5 V to 2 V as the temperature increases from 25°C to 225°C, while its breakdown voltage increases from -23 V to -19 V. At 300°C, the drain current of the cascode switch is 21.4% of its 25°C value, which agrees well with the reduction of the 4H-SiC electron mobility with temperature. The VJFET based all-SiC cascode switch is normally-off at 300°C, with its threshold voltage shifting from 1.6 V to 0.9 V as the temperature increases from 25°C to 300°C. This agrees well with the measured reduction in VJFET built-in potential. Finally, the reduction in cascode transconductance with temperature follows that of the theoretical 4H-SiC electron mobility. Overall, the measured thermally-induced cascode parameter shifts are in excellent agreement with theory, which signifies fabrication of robust SiC VJFETs for power switching applications.

Download Full-text