scholarly journals Layout Strengthening the ESD Performance for High-Voltage N-Channel Lateral Diffused MOSFETs

Electronics ◽  
2020 ◽  
Vol 9 (5) ◽  
pp. 718
Author(s):  
Sheng-Kai Fan ◽  
Shen-Li Chen ◽  
Po-Lin Lin ◽  
Hung-Wei Chen
Keyword(s):  
Schottky Diode ◽  
High Voltage ◽  
Low Voltage ◽  
Channel Width ◽  
Drift Region ◽  
Operating Voltage ◽  
Equivalent Series Resistance ◽  
Drain Side ◽  
Region Length ◽  
Latch Up

An electrostatic discharge (ESD) event can negatively affect the reliability of integrated circuits. Therefore, improving on ESD immunity in high-voltage (HV) n-channel (n) lateral diffused metal–oxide–semiconductor field-effect transistor (HV nLDMOS) components through drain-side layout engineering was studied. This involved adjusting the operating voltage, improving the non-uniform turned-on phenomenon, and examining the effects of embedded-device structures on ESD. All proposed architectures for improving ESD immunity in this work were measured and evaluated using a transmission-line pulse system. The corresponding trigger voltage (Vt1), holding voltage (Vh) and secondary breakdown current (It2) results of the tested devices were obtained. This paper first addresses the drift-region length modulation to design different operating voltages, which decreased as the drift region length and shallow trench isolation (STI) length shrunk. When an HV nLDMOS device decreased to the shortest drift region length, the Vt1 and Vh values were closest to 21.85, and 9.27 V, respectively. The It2 value of a low-voltage operated device could be increased to a maximum value of 3.25 A. For the channel width modulation, increasing the layout finger number of an HV LDMOS device did not really help the ESD immunity that because it may suffer the problem of non-uniform turned-on phenomenon. Therefore, adjusting the optimized channel width was the best one method of improvement. Furthermore, to improve the low ESD reliability problem of nLDMOS devices, two structures were used to improve the ESD capability. The first was a drain side—embedded silicon-controlled rectifier (SCR). Here, the SCR PNP-arranged type in the drain side had the best ESD capability because the SCR path was short and had been prior to triggering; however, it also has a latch-up risk and low Vh characteristic. By removing the entire heavily doped drain-side N+ region, the equivalent series resistance in the drain region was increased, so that the It2 performance could be increased from 2.29 A to 3.98 A in the structure of a fully embedded drain-side Schottky diode. This component still has sufficiently high Vh behaviour. Therefore, embedding a full Schottky-diode into an HV nLDMOS in the drain side was the best method and was efficient for improving the ESD/Latch-up abilities of the device. The figure of merit (FOM) of ESD, Latch-up, and cell area considerations improved to approximately 80.86%.

High Voltage and Fast Switching Reverse Recovery Characteristics of 4H-SiC PiN Diode

2014 ◽  
Vol 778-780 ◽  
pp. 841-844 ◽  
Author(s):  
Koji Nakayama ◽  
Shuji Ogata ◽  
Toshihiko Hayashi ◽  
Tetsuro Hemmi ◽  
Atsushi Tanaka ◽  
...  
Keyword(s):  
High Voltage ◽  
Recovery Time ◽  
Carrier Lifetime ◽  
Low Voltage ◽  
Reduction Rate ◽  
Drift Region ◽  
Pin Diode ◽  
Fully Depleted ◽  
Fast Switching ◽  
Reverse Recovery Time

The reverse recovery characteristics of a 4H-SiC PiN diode under higher voltage and faster switching are investigated. In a high-voltage 4H-SiC PiN diode, owing to an increased thickness, the drift region does not become fully depleted at a relatively low voltage Furthermore, an electron–hole recombination must be taken into account when the carrier lifetime is equal to or shorter than the reverse recovery time. High voltage and fast switching are therefore needed for accurate analysis of the reverse recovery characteristics. The current reduction rate increases up to 2 kA/μs because of low stray inductance. The maximum reverse voltage during the reverse recovery time reaches 8 kV, at which point the drift layer is fully depleted. The carrier lifetime at the high level injection is 0.086 μs at room temperature and reaches 0.53 μs at 250 °C.

scholarly journals Robust ESD-Reliability Design of 300-V Power N-Channel LDMOSs with the Elliptical Cylinder Super-Junctions in the Drain Side

Electronics ◽  
2020 ◽  
Vol 9 (5) ◽  
pp. 730 ◽  
Author(s):  
Shen-Li Chen ◽  
Pei-Lin Wu ◽  
Yu-Jen Chen
Keyword(s):  
High Voltage ◽  
Field Effect Transistors ◽  
Area Ratio ◽  
Operating Conditions ◽  
Elliptical Cylinder ◽  
Drift Region ◽  
Reference Device ◽  
Drain Side ◽  
Drain Region ◽  
Original Reference

The weak ESD-immunity problem has been deeply persecuted in ultra high-voltage (UHV) metal-oxide-semiconductor field-effect transistors (MOSFETs) and urgently needs to be solved. In this paper, a UHV 300 V circular n-channel (n) lateral diffused MOSFET (nLDMOS) is taken as the benchmarked reference device for the electrostatic discharge (ESD) capability improvement. However, a super-junction (SJ) structure in the drain region will cause extra depletion zones in the long drain region and reduce the peak value of the channel electric field. Therefore, it may directly increase the resistance of the device to ESD. Then, in this reformation project for UHV nLDMOSs to ESD, two strengthening methods were used. Firstly, the SJ area ratio changed by the symmetric eight-zone elliptical-cylinder length (X) variance (i.e., X = 5, 10, 15 and 20 μm) is added into the drift region of drain side to explore the influence on ESD reliability. From the experimental results, it could be found that the breakdown voltages (VBK) were changed slightly after adding this SJ structure. The VBK values are filled between 391 and 393.5 V. Initially, the original reference sample is 393 V; the VBK changing does not exceed 0.51%, which means that these components can be regarded as little changing in the conduction characteristic after adding these SJ structures under the normal operating conditions. In addition, in the ESD transient high-voltage bombardment situation, the human-body model (HBM) capability of the original reference device is 2500 V. Additionally, as SJs with the length X high-voltage P-type well (HVPW) are inserted into the drain-side drift region, the HBM robustness of these UHV nLDMOSs increases with the length X of the HVPW. When the length X (HVPW) is 20 μm, the HBM value can be upgraded to a maximum value of 5500 V, the ESD capability is increased by 120%. A linear relationship between the HBM immunity level and area ratio of SJs in the drains side in this work can be extracted. The second part revealed that, in the symmetric four-zone elliptical cylinder SJ modulation, the HBM robustness is generally promoted with the increase of HVPW SJ numbers (the highest HBM value (4500 V) of the M5 device improved by 80% as compared with the reference device under test (DUT)). Therefore, from this work, we can conclude that the addition of symmetric elliptical-cylinder SJ structures into the drain-side drift region of a UHV nLDMOS is a good strategy for improving the ESD immunity.

Impacts of ESD Reliability by Different Layout Engineering in the 0.25-μm 60-V High-Voltage LDMOS Devices

2018 ◽  
Vol 3 (2) ◽  
Author(s):  
Shen-Li Chen ◽  
Chun-Ju Lin ◽  
Huang Yu-Ting
Keyword(s):  
Metal Oxide ◽  
High Voltage ◽  
Electrostatic Discharge ◽  
Complementary Metal Oxide Semiconductor ◽  
Narrow Channel ◽  
Metal Oxide Semiconductor ◽  
Channel Width ◽  
Oxide Semiconductor ◽  
Drain Side ◽  
Better Than

Abstract How to effectively enhance the reliability robustness in high-voltage (HV) BCD [(bipolar) complementary metal-oxide semiconductor (CMOS) diffusion metaloxide semiconductor (DMOS)] processes is an important issue. Influences of layouttype dependences on anti-electrostatic discharge (ESD) robustness in a 0.25-μm 60-V process will be studied in this chapter, which includes, in part (1), the traditional striped-type n-channel lateral-diffused MOSFET (nLDMOS), waffle-type nLDMOS, and nLDMOS embedded with a “p-n-p”-arranged silicon-controlled rectifier (SCR) devices in the drain side; and in part (2) a p-channel LDMOS (pLDMOS) with an embedded “p-n-p-n-p”-arranged-type SCR in the drain side (diffusion regions of the drain side is P+-N+-P+-N+-P+). Then, these LDMOS devices are used to evaluate the influence of layout architecture on trigger voltage (Vt1), holding voltage (Vh), and secondary breakdown current (It2). Eventually, the sketching of the layout pattern of a HV LDMOS is a very important issue in the anti-ESD consideration. Also, in part (1), the waffle-type nLDMOS DUT contributes poorly to It2 robustness due to the non-uniform turned-on phenomenon and a narrow channel width per unit finger. Therefore, the It2 robustness of a waffle-type nLDMOS device is decreased about 17% as compared to a traditional striped-type nLDMOS device (reference DUT-1). The ESD abilities of traditional stripedtype and waffle-type nLDMOS devices with an embedded SCR (“p-n-p”-manner arrangement in the drain side) are better than a traditional nLDMOS 224.4% in average. Noteworthy, the nLDMOS-SCR with the “p-n-p” -arranged-type in the drainend is a good structure for the anti-ESD reliability especially in HV usages. Furthermore, in part (2) this layout manner of P+ discrete-island distributions in the drain-side have some impacts on the anti-ESD and anti-latch-up (LU) immunities. All of their It2 values have reached above 6 A; however, the major repercussion is that the Vh value will be decreased about 66.7 ~ 73.7%.

Towards High-Voltage MOSFETs in Ultrathin FDSOI

2016 ◽  
Vol 25 (01n02) ◽  
pp. 1640005 ◽  
Author(s):  
Antoine Litty ◽  
Sylvie Ortolland ◽  
Dominique Golanski ◽  
Christian Dutto ◽  
Alexandres Dartigues ◽  
...  
Keyword(s):  
High Voltage ◽  
Low Voltage ◽  
Ground Plane ◽  
Silicon Film ◽  
Silicon On Insulator ◽  
Drift Region ◽  
Back Gate ◽  
Fully Depleted ◽  
Buried Oxide ◽  
Core Technology

High-Voltage MOSFETs are essential devices for complementing and extending the domains of application of any core technology including low-power, low-voltage CMOS. In this paper, we propose and describe advanced Extended-Drain MOSFETs, designed, processed and characterized in ultrathin body and buried oxide Fully Depleted Silicon on Insulator technology (UTBB-FDSOI). These transistors have been implemented in two technology nodes (28 nm and 14 nm) with different silicon film and buried oxide thicknesses (TSi < 10nm and TBOX ≤ 25nm). Our innovative concept of Dual Ground Plane (DGP) provides RESURF-like effect (reduced surface field) and offers additional flexibility for HVMOS integration directly in the ultrathin film of the FDSOI wafer. In this configuration, the primary back-gate controls the threshold voltage (VTH) to ensure performance and low leakage current. The second back-gate, located underneath the drift region, acts as a field plate enabling the improvement of the ON resistance (RON) and breakdown voltage (BV). The trade-off RON.S versus BV is investigated as a function of doping level, length and thickness of the drift region. We report promising results and discuss further developments for successful integration of high-voltage MOSFETs in ultrathin CMOS FDSOI technology.

scholarly journals METHODS OF ADJUSTING FORMING LINES USING A LOW VOLTAGE THYRISTOR SWITCH

2021 ◽  
pp. 135-138
Author(s):  
O.I. Kosoi ◽  
V.O. Mats ◽  
V.V. Mytrochenko ◽  
V.Yu. Titov ◽  
Yu.D. Tur ◽  
...  
Keyword(s):  
High Voltage ◽  
Voltage Pulse ◽  
Low Voltage ◽  
Operating Mode ◽  
High Voltage Pulse ◽  
Fine Tuning ◽  
Operating Voltage ◽  
Thyristor Switch ◽  
Pulse Modulator ◽  
Optimal Value

A method of adjusting the generating lines of a high-voltage pulse modulator with a thyristor switch at a charg-ing voltage of 150 V is given. The degree of pre-distortion is determined to obtain in the operating mode (60 kV) a voltage pulse with the required non-uniformity at the optimal value of the degaussing current of the trans-former. An element of fine tuning of forming lines at operating voltage is developed and applied.

scholarly journals Implementation of Low Voltage MOSFET and Power LDMOS on InGaAs

2021 ◽  
Author(s):  
MANOJ SINGH ADHIKARI ◽  
Raju Patel ◽  
Yogesh Kumar Verma ◽  
Yashvir Singh
Keyword(s):  
High Voltage ◽  
Low Voltage ◽  
Vertical Direction ◽  
Drain Current ◽  
Drift Region ◽  
Short Channel ◽  
Isolation Technique ◽  
Dg Mosfet ◽  
Dual Channels ◽  
Dual Gate

Abstract In this paper, a new low voltage MOSFET (LV MOSFET) and high voltage dual-gate MOSFET (HV DG MOSFET) have been proposed with concept of integration based on trench technology on InGaAs material. Junction isolation technique is used for the implementation of a low voltage MOSFET and a high power dual gate MOSFET in same InGaAs epitaxial layer side by side. The HV DG MOSFET consists of dual gate that are placed in drift region under the oxide-filled trenches. The proposed structure minimize on-resistance (R on ) along with increased breakdown voltage (V br ) due to enhanced RESURF effect, the creation of dual channels, and due to folding technique of drift region in vertical direction. In the HV DG MOSFET, the drain current (I D ) increases leading to enhanced transconductance (gm) by simultaneous conduction of channels with improved maximum oscillation frequency (f max ) and cut-off frequency (f t ). On the other side, the low voltage MOSFET consists of a gate placed in a centre of the structure within an oxide trench to create two n-channels in the p-base. The two channels are conducting in parallel and give substantial enhancement in peak g m , I D , f max and f t with more control over the short channel parameters. The design and performance analysis of low voltage MOSFET (LV MOSFET) and high voltage dual-gate MOSFET (HV DG MOSFET) are carried out on 2-D ATLAS device simulator.

Toward High-Resolution Low-Voltage SEM

1988 ◽  
Vol 46 ◽  
pp. 218-219
Author(s):  
Zhifeng Shao
Keyword(s):  
Low Voltage ◽  
Spherical Aberration ◽  
Chromatic Aberration ◽  
Limiting Factor ◽  
Operating Voltage ◽  
Probe Radius ◽  
Non Local ◽  
Electron Microscopes ◽  
Image Position ◽  
Scanning Electron Microscopes

Recently, low voltage (≤5kV) scanning electron microscopes have become popular because of their unprecedented advantages, such as minimized charging effects and smaller specimen damage, etc. Perhaps the most important advantage of LVSEM is that they may be able to provide ultrahigh resolution since the interaction volume decreases when electron energy is reduced. It is obvious that no matter how low the operating voltage is, the resolution is always poorer than the probe radius. To achieve 10Å resolution at 5kV (including non-local effects), we would require a probe radius of 5∽6 Å. At low voltages, we can no longer ignore the effects of chromatic aberration because of the increased ratio δV/V. The 3rd order spherical aberration is another major limiting factor. The optimized aperture should be calculated as

Low-Voltage Variable Gain Current Amplifier for High-Voltage Signal Processing

2009 ◽  
Vol 129 (8) ◽  
pp. 1511-1517
Author(s):  
Nicodimus Retdian ◽  
Jieting Zhang ◽  
Takahide Sato ◽  
Shigetaka Takagi
Keyword(s):  
Signal Processing ◽  
High Voltage ◽  
Low Voltage ◽  
Current Amplifier ◽  
Variable Gain ◽  
Voltage Signal
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