scholarly journals Physics Based Analytical Modeling of Asymmetric Elevated Source Tunnel FET (AES-TFET) for Better Tunnel Junction Device (TJD) Performance

2021 ◽  
Keyword(s):  
Tunnel Junction ◽  
Analytical Modeling ◽  
Tunnel Fet ◽  
Junction Device ◽  
Elevated Source

Abstract The authors have requested that this preprint be withdrawn due to erroneous posting.

scholarly journals Physics Based Analytical Modeling of Asymmetric Elevated Source Tunnel FET (AES-TFET) for Better Tunnel Junction Device (TJD) Performance

2021 ◽  
Author(s):  
RITAM DUTTA ◽  
T.D. Subash ◽  
Nitai Paitya
Keyword(s):  
Tunnel Junction ◽  
Carrier Transport ◽  
Analytical Modelling ◽  
Field Variation ◽  
Corner Effect ◽  
Junction Device ◽  
Electric Field Variation ◽  
Effect Transistor ◽  
Numerical Device ◽  
Elevated Source

Abstract In this paper, a two-dimensional analytical model for asymmetric elevated source tunnel field effect transistor (AES-TFET) has been developed to obtain better tunnel junction device performance. Device physics based analytical modelling is performed by solving 2-D Poisson’s equation. Surface potential distribution, electric field variation and band-to-band tunneling (B2B) rate have been investigated by this numerical modelling. In our proposed structure, the source has been elevated (varied 2 nm to 6 nm) to incorporate corner effect; which boosts the carrier transport via thin tunneling barrier, with controlled ambipolar conduction. This eventually produces better source-channel interface tunneling for a n-channel AES-TFET structure. 2-D numerical device simulator (SILVACO TCAD) has been used for simulation work. The simulated graphical representations have been finally validated by analytical modelling of AES-TFET.

Reliable majority voter based on spin transfer torque magnetic tunnel junction device

2016 ◽  
Vol 52 (1) ◽  
pp. 47-49 ◽  
Author(s):  
P.F. Butzen ◽  
M. Slimani ◽  
Y. Wang ◽  
H. Cai ◽  
L.A.B. Naviner
Keyword(s):  
Tunnel Junction ◽  
Magnetic Tunnel Junction ◽  
Spin Transfer Torque ◽  
Spin Transfer ◽  
Junction Device ◽  
Majority Voter

scholarly journals Structural Size Effect with Altered Temperature on MgO-based Magnetic Tunnel Junction Device During Current Flow

2016 ◽  
Vol 86 ◽  
pp. 200-203 ◽  
Author(s):  
Veeraporn Pomsanam ◽  
Chanon Warisarn ◽  
Apirat Siritaratiwat ◽  
Chayada Surawanitkun
Keyword(s):  
Size Effect ◽  
Tunnel Junction ◽  
Current Flow ◽  
Magnetic Tunnel Junction ◽  
Structural Size ◽  
Junction Device

Device physics based analytical modeling for electrical characteristics of single gate extended source tunnel FET (SG-ESTFET)

2020 ◽  
Vol 148 ◽  
pp. 106725
Author(s):  
Jagritee Talukdar ◽  
Gopal Rawat ◽  
Bijit Choudhuri ◽  
Kunal Singh ◽  
Kavicharan Mummaneni
Keyword(s):  
Analytical Modeling ◽  
Device Physics ◽  
Electrical Characteristics ◽  
Extended Source ◽  
Tunnel Fet

An Accurate Drain Current Model for Symmetric Dual Gate Tunnel FET Using Effective Tunneling Length

2018 ◽  
Vol 9 (1) ◽  
pp. 85-91 ◽  
Author(s):  
Sasmita Sahoo ◽  
Sidhartha Dash ◽  
Guru P. Mishra
Keyword(s):  
Performance Indicators ◽  
Analytical Modeling ◽  
Present Model ◽  
Current Model ◽  
Practical Importance ◽  
Drain Current ◽  
Subthreshold Slope ◽  
Tunnel Fet ◽  
Dual Gate ◽  
Tcad Sentaurus

Introduction: Here we propose an accurate drain current model for a Symmetric Dual Gate Tunnel FET (SDG-TFET) using effective tunneling length and generation rate of carrier over tunneling junction area. Analytical Modeling: The surface potential of the model is obtained by solving 2-dimensional Poisson’s equation and further extends to determine the magnitude of initial tunneling length and final tunneling length. The different DC performance indicators like drain current (ID), threshold voltage (Vth), transconductance (gm) and Subthreshold Slope (SS) for the present model are extensively investigated and the results are compared with that of Single Gate Tunnel FET (SGTFET). Conclusion: The practical importance of this model relies on its accuracy and improved electrostatic performance over SG-TFET. The analytical model results are validated using TCAD Sentaurus (Synopsys) device simulator.

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