scholarly journals Physics Based Analytical Modeling of Asymmetric Elevated Source Tunnel FET (AES-TFET) for Better Tunnel Junction Device (TJD) Performance

Author(s):  
RITAM DUTTA ◽  
T.D. Subash ◽  
Nitai Paitya

Abstract In this paper, a two-dimensional analytical model for asymmetric elevated source tunnel field effect transistor (AES-TFET) has been developed to obtain better tunnel junction device performance. Device physics based analytical modelling is performed by solving 2-D Poisson’s equation. Surface potential distribution, electric field variation and band-to-band tunneling (B2B) rate have been investigated by this numerical modelling. In our proposed structure, the source has been elevated (varied 2 nm to 6 nm) to incorporate corner effect; which boosts the carrier transport via thin tunneling barrier, with controlled ambipolar conduction. This eventually produces better source-channel interface tunneling for a n-channel AES-TFET structure. 2-D numerical device simulator (SILVACO TCAD) has been used for simulation work. The simulated graphical representations have been finally validated by analytical modelling of AES-TFET.

2021 ◽  
Author(s):  
RITAM DUTTA ◽  
T.D. Subash ◽  
Nitai Paitya

Abstract A two-dimensional analytical model for asymmetric extended source tunnel field effect transistor (AES-TFET) has been developed to obtain better device performance. The proposed device model has been analytically modelled and performed by solving 2-D Poisson’s equation. Surface potential distribution, electric field variation and band-to-band tunneling (BTBT) rate have been investigated by this numerical modelling. The source region of novel structure of TFET has been extended (varied 2 nm to 6 nm) to incorporate corner effect, which allows BTBT through a thin tunneling barrier, with controlled ambipolar conduction. This eventually produces better source-channel interface tunneling for a n-channel AES-TFET. 2-D numerical device simulator (SILVACO TCAD) has been used for simulation work. The simulated work has been finally validated by analytical modelling of AES-TFET. Better ION, IOFF and switching ratio has been obtained from this novel TFET structure.


Nanoscale ◽  
2019 ◽  
Vol 11 (37) ◽  
pp. 17368-17375 ◽  
Author(s):  
Inyong Moon ◽  
Sungwon Lee ◽  
Myeongjin Lee ◽  
Changsik Kim ◽  
Daehee Seol ◽  
...  

WSe2 FET oxidized by plasma. Channel resistance decreases exponentially with increasing WSe2 work function, approaching thermal limit.


2020 ◽  
Vol 19 ◽  
pp. 168-171 ◽  
Author(s):  
Kitae Lee ◽  
Junil Lee ◽  
Sihyun Kim ◽  
Ryoongbin Lee ◽  
Soyoun Kim ◽  
...  

2013 ◽  
Vol 56 (6) ◽  
pp. 721-730
Author(s):  
AN Zhang-Hui ◽  
DU Xue-Bin ◽  
TAN Da-Cheng ◽  
FAN Ying-Ying ◽  
LIU Jun ◽  
...  

2016 ◽  
Vol 52 (1) ◽  
pp. 47-49 ◽  
Author(s):  
P.F. Butzen ◽  
M. Slimani ◽  
Y. Wang ◽  
H. Cai ◽  
L.A.B. Naviner

2016 ◽  
Vol 86 ◽  
pp. 200-203 ◽  
Author(s):  
Veeraporn Pomsanam ◽  
Chanon Warisarn ◽  
Apirat Siritaratiwat ◽  
Chayada Surawanitkun

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