Software Design of Veriloghdl Code Generation for Ladder Diagram and Data Acquisition Using LABVIEW

2021 ◽  
Author(s):  
G Dhanabalan ◽  
Tamil Selvi S
Keyword(s):  
Data Acquisition ◽  
Code Generation ◽  
High Speed ◽  
Ladder Diagram ◽  
Digital Signals ◽  
Traffic Light ◽  
Process Industries ◽  
Concurrent Execution ◽  
Scan Time ◽  
Field Programmable

Abstract The powerful advantages of programmable logic controller (PLC) dominate the process industries. Scan time of the PLC increases with the number of inputs, rungs added in ladder diagram (LD). Researchers have identified and proved that field programmable gate array (FPGA) is more suitable than PLC for high speed applications. PLC executes the instructions represented through LD. FPGA does not support LD. PLC programmers are not familiar with FPGA programming. This work has developed application software to generate equivalent VerilogHDL code for LD using LabVIEW. Novelty in this work is that each rung is defined using an "assign" statement to ensure concurrent execution of all the rungs. A data acquisition system was created to monitor the digital signals handled by the FPGA. The software was verified with a case study of substances mixing and traffic light control system.

scholarly journals High speed multi-channel data acquisition technique for efficient hardware utilization using quad data rate approach

2018 ◽  
Vol 7 (4) ◽  
pp. 2569
Author(s):  
Priyanka Chauhan ◽  
Dippal Israni ◽  
Karan Jasani ◽  
Ashwin Makwana
Keyword(s):  
Power Consumption ◽  
Data Acquisition ◽  
Resource Utilization ◽  
Field Programmable Gate Array ◽  
High Speed ◽  
State Of The Art ◽  
Data Rate ◽  
Field Programmable ◽  
Sensor Signals ◽  
Acquisition Technique

Data acquisition is the most demanding application for the acquisition and monitoring of various sensor signals. The data received are processed in real-time environment. This paper proposes a novel Data Acquisition (DAQ) technique for better resource utilization with less power consumption. Present work has designed and compared advanced Quad Data Rate (QDR) technique with traditional Dual Data Rate (DDR) technique in terms of resource utilization and power consumption of Field Programmable Gate Array (FPGA) hardware. Xilinx ISE is used to verify results of FPGA resource utilization by QDR with state of the art DDR approach. The paper ratiocinates that QDR technique outperforms traditional DDR technique in terms of FPGA resource utilization.  

Design and Test of High Speed Digitization Sampling Circuit Based on FPGA

2013 ◽  
Vol 482 ◽  
pp. 386-389
Author(s):  
Peng Qin ◽  
Hao Lu ◽  
Zhi Ye Jiang ◽  
Jin Liang Bai ◽  
Lu Gao ◽  
...  
Keyword(s):  
Data Acquisition ◽  
Circuit Design ◽  
Field Programmable Gate Array ◽  
High Speed ◽  
Engineering Practice ◽  
Excellent Performance ◽  
Field Programmable ◽  
High Speed Data Acquisition ◽  
High Speed Data ◽  
Data Acquisition Program

To sample wideband IF signal with large amounts of data, a high-speed data acquisition program is presented. The program focus on circuit design, issues that need attention, and high-speed sampling signal deceleration strategy. The 2.4GHz rate sampling data acquisition, reception and demux are completed with ADC083000 and Field-Programmable Gate Array (FPGA). At last, a result of sampling with the converter is offered by chipscope software. The result verified ADC083000 has an excellent performance with more than 6.5 bit ENOB and good phase coherence. In engineering practice, the design has been used and has good performance.

Design and Realization of High-Speed and Real-Time Signal Processing System Based on FPGA

2011 ◽  
Vol 128-129 ◽  
pp. 1382-1385
Author(s):  
Xin Chun Wang ◽  
Yue Hong Peng ◽  
Man Cheng ◽  
Kai Hua Yue
Keyword(s):  
High Speed ◽  
Processing System ◽  
Time Signal ◽  
Digital Signals ◽  
Signal Processing System ◽  
Signal Collection ◽  
Field Programmable ◽  
High Speed Data ◽  
Rapid Processing ◽  
Control Complex

We usually adopt DSP and ARM to perform signal collection and processing. However, functions of DSP and ARM largely depend on the software. Parameter modulation of the software must account for sampling time partly. Moreover, software can not control complex peripheral logic circuit very well. The above problems render DSP and ARM containing big flaws in high-speed data collection and processing. Field-programmable Gate Array (FPGA) possesses the characteristics of timeliness, controllability and rapid processing speed. The paper designed a new circuit based on FPGA to obtain high-speed signal, and utilized FFT IP core in FPGA to perform spectral analysis with the help of digital signals from the circuit. The paper introduced the design based on FPGA and verified that it possesses good performance according to actual experiments.

The Data Acquisition of High Speed A/D Conversion Based on STC12C5A32S2 SCM

2012 ◽  
Vol 182-183 ◽  
pp. 670-675
Author(s):  
Cheng Ying Wu ◽  
Zhan You Fan ◽  
Hong Jiao Ma ◽  
Zai Min He ◽  
Zhao Ming Wang
Keyword(s):  
Data Acquisition ◽  
High Speed ◽  
Low Cost ◽  
High Accuracy ◽  
Single Chip ◽  
Digital Signals ◽  
Single Chip Microcomputer ◽  
Display Module ◽  
Analog Signals ◽  
Lcd Display

In order to achieve high-accuracy, high speed and low cost A/D conversion, a new design based on STC12C5A32S2 single-chip microcomputer (SCM) is given. Compared with the previous A/D conversion, the biggest advantage is that the paper combine software with hardware and it can adjust the speed of transformation through procedure.We don't need to modify circuit, just need to modify signals of input and procedures. So the flexibility of A/D conversion can be enhanced, also saved costs. The design mainly makes use of new function of STC12C5A32S2 SCM to realize conversion between analog signals and digital signals. In order that researchers can analyze and use the convention results, the design add a LCD display module. The paper primarily analyses the design of circuit and interface technology between the SCM and other chips. Also, the peculiar function of STC, the LCD display method of LMB202DDC and the flow of software are expounded in detail. The simulation result based on Proteus is given by the end of paper.

Design of Data Acquisition System Based on FPGA

2011 ◽  
Vol 403-408 ◽  
pp. 1592-1595
Author(s):  
Guo Sheng Xu
Keyword(s):  
Data Processing ◽  
Data Acquisition ◽  
Real Time ◽  
High Speed ◽  
Image Data ◽  
Data Acquisition System ◽  
Acquisition System ◽  
Time Data ◽  
Real Time Processing ◽  
Field Programmable

A new kind of data acquisition system is introduced in this paper, in which the multi-channel synchronized real-time data acquisition under the coordinate control of field-programmable gate array(FPGA) is realized. The design uses field programmable gate arrays(FPGA) for the data processing and logic control. For high speed CCD image data processing, the paper adopts regional parallel processing based on FPGA. The FPGA inner block RAM is used to build high speed image data buffer is put into operation to achieve high speed image data integration and real-time processing. The proposed data acquisition system has characteristics of stable performance, flexible expansion, high real-timeness and integration

scholarly journals Ultra-high Speed and Dual-Channel Data Acquisition Card with 1GSPS Based on PXI Bus

2018 ◽  
Vol 2 (1) ◽  
pp. 22
Author(s):  
Pengyun Zhang ◽  
Henan Guo
Keyword(s):  
Data Acquisition ◽  
High Speed ◽  
Sampling Rate ◽  
Random Access ◽  
Dual Channel ◽  
Ultra High Speed ◽  
Field Programmable ◽  
Data Acquisition Card ◽  
And Control ◽  
Test Result

This paper discusses the chief techniques and design principles of an ultra-high speed and dual-channel data acquisition card based on PXI bus, using FPGA (Field Programmable Gate Array) as logic controller cell. The instrument consists of pre-process circuit, A/D converter, SDRAM (Synchronous Dynamic random access memory), and control circuit integrated in FPGA. It can achieve allowing up to 1000MHz real-time sampling rate. The test result indicates that the system works normally and the system design is successful.

Accelerating laser processes with a smart two-dimensional polygon mirror scanner for ultra-fast beam deflection

2021 ◽  
Vol 0 (0) ◽  
Author(s):  
Florian Roessler ◽  
André Streek
Keyword(s):  
Energy Distribution ◽  
Real Time ◽  
Laser Processing ◽  
High Speed ◽  
Beam Deflection ◽  
Two Dimensional ◽  
Heat Accumulation ◽  
Field Programmable ◽  
Drill Holes ◽  
Average Laser

Abstract In laser processing, the possible throughput is directly scaling with the available average laser power. To avoid unwanted thermal damage due to high pulse energy or heat accumulation during MHz-repetition rates, energy distribution over the workpiece is required. Polygon mirror scanners enable high deflection speeds and thus, a proper energy distribution within a short processing time. The requirements of laser micro processing with up to 10 kW average laser powers and high scan speeds up to 1000 m/s result in a 30 mm aperture two-dimensional polygon mirror scanner with a patented low-distortion mirror configuration. In combination with a field programmable gate array-based real-time logic, position-true high-accuracy laser switching is enabled for 2D, 2.5D, or 3D laser processing capable to drill holes in multi-pass ablation or engraving. A special developed real-time shifter module within the high-speed logic allows, in combination with external axis, the material processing on the fly and hence, processing of workpieces much larger than the scan field.

Based on FPGA Intelligent Physiological Parameters Acquisition

2013 ◽  
Vol 344 ◽  
pp. 107-110
Author(s):  
Shun Ren Hu ◽  
Ya Chen Gan ◽  
Ming Bao ◽  
Jing Wei Wang
Keyword(s):  
High Speed ◽  
Low Cost ◽  
Physiological Parameters ◽  
Sensor Data ◽  
Low Power Consumption ◽  
Physiological Signal ◽  
Pulse Sensor ◽  
Monitoring Applications ◽  
Field Programmable ◽  
Design Ideas

For the physiological signal monitoring applications, as a micro-controller based on field programmable gate array (FPGA) physiological parameters intelligent acquisition system is given, which has the advantages of low cost, high speed, low power consumption. FPGA is responsible for the completion of pulse sensor, the temperature sensor, acceleration sensor data acquisition and serial output and so on. Focuses on the design ideas and architecture of the various subsystems of the whole system, gives the internal FPGA circuit diagram of the entire system. The whole system is easy to implement and has a very good promotional value.

Sign in / Sign up

Export Citation Format

Share Document