Military Specification, Modules, Standard Electronic Memory Array, 128K Dynamic Random Access Module, Key Code JEJ

2008 ◽

Author(s):

Steven B. Herschbein ◽

Hyoung H. Kang ◽

Scott L. Jansen ◽

Andrew S. Dalton

Keyword(s):

Flip Chip ◽

Focused Ion Beam ◽

Ion Beam ◽

Random Access ◽

Cell Counting ◽

Test Results ◽

Laboratory Procedure ◽

Memory Array ◽

Dual Beam ◽

Process Level

Abstract Test engineers and failure analyst familiar with random access memory arrays have probably encountered the frustration of dealing with address descrambling. The resulting nonsequential internal bit cell counting scheme often means that the location of the failing cell under investigation is nowhere near where it is expected to be. A logical to physical algorithm for decoding the standard library block might have been provided with the design, but is it still correct now that the array has been halved and inverted to fit the available space in a new processor chip? Off-line labs have traditionally been tasked with array layout verification. In the past, hard and soft failures could be induced on the frontside of finished product, then bitmapped to see if the sites were in agreement. As density tightened, flip-chip FIB techniques to induce a pattern of hard fails on packaged devices came into practice. While the backside FIB edit method is effective, it is complex and expensive. The installation of an in-line Dual Beam FIB created new opportunities to move FA tasks out of the lab and into the FAB. Using a new edit procedure, selected wafers have an extensive pattern of defects 'written' directly into the memory array at an early process level. Bitmapping of the RAM blocks upon wafer completion is then used to verify correlation between the physical damaged cells and the logical sites called out in the test results. This early feedback in-line methodology has worked so well that it has almost entirely displaced the complex laboratory procedure of backside FIB memory array descramble verification.

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Ge 1 Sb 2 Te 4 Based Chalcogenide Random Access Memory Array Fabricated by 0.18-μm CMOS Technology

Chinese Physics Letters ◽

10.1088/0256-307x/24/3/056 ◽

2007 ◽

Vol 24 (3) ◽

pp. 790-792 ◽

Cited By ~ 4

Author(s):

Zhang Ting ◽

Song Zhi-Tang ◽

Feng Gao-Ming ◽

Liu Bo ◽

Wu Liang-Cai ◽

...

Keyword(s):

Random Access ◽

Random Access Memory ◽

Cmos Technology ◽

Access Memory ◽

Memory Array

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A SPICE Model of Resistive Random Access Memory for Large-Scale Memory Array Simulation

IEEE Electron Device Letters ◽

10.1109/led.2013.2293354 ◽

2014 ◽

Vol 35 (2) ◽

pp. 211-213 ◽

Cited By ~ 70

Author(s):

Haitong Li ◽

Peng Huang ◽

Bin Gao ◽

Bing Chen ◽

Xiaoyan Liu ◽

...

Keyword(s):

Large Scale ◽

Random Access ◽

Random Access Memory ◽

Resistive Random Access Memory ◽

Access Memory ◽

Memory Array ◽

Spice Model

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IMAP: INTEGRATED MEMORY ARRAY PROCESSOR

Journal of Circuits System and Computers ◽

10.1142/s0218126692000155 ◽

1992 ◽

Vol 02 (03) ◽

pp. 227-245 ◽

Cited By ~ 14

Author(s):

YOSHIHIRO FUJITA ◽

NOBUYUKI YAMASHITA ◽

SHIN-ICHIRO OKAZAKI

Keyword(s):

Random Access ◽

Memory Cell ◽

Processor Array ◽

Array Processor ◽

Single Chip ◽

Access Memory ◽

One Dimensional ◽

Memory Array ◽

Architectural Features ◽

Simd Processing

This paper presents architectural features and performances for an Integrated Memory Array Processor (IMAP) LSI, which integrates a large capacity memory and a one-dimensional SIMD processor array on a single chip. The IMAP has a conventional memory interface, almost the same as a dual port video RAM with operational input extension. SIMD processing is carried out on the IMAP chip, using an internal processor array, while other higher level processing is concurrently accomplished with external processors through the random access memory port. In addition to the basic IMAP architecture, this paper describes orthogonal IMAP, which has an extended IMAP architecture. The basic IMAP uses a conventional memory cell, while the orthogonal IMAP uses an orthogonal memory for holding images.

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Highly Reliable Memory Operation of High Density Three-Terminal Thyristor Random Access Memory

10.21203/rs.3.rs-585213/v2 ◽

2021 ◽

Author(s):

Hyangwoo Kim ◽

Hyeonsu Cho ◽

Hyeon-Tak Kwak ◽

Myunghae Seo ◽

Seungho Lee ◽

...

Keyword(s):

Random Access ◽

Random Access Memory ◽

High Density ◽

Data Retention ◽

Access Memory ◽

Cathode Voltage ◽

Cross Point ◽

Memory Array ◽

Retention Characteristics ◽

Power Operation

Abstract Three-terminal (3-T) thyristor random-access memory is explored for a next generation high-density nanoscale vertical cross-point array. The effects of standby voltages on the device are thoroughly investigated in terms of gate-cathode voltage (VGC,ST) and anode- cathode voltage (VAC,ST) in the standby state for superior data retention characteristics and low-power operation. The device with the optimized VGC,ST of -0.4 V and VAC,ST of 0.6 V shows the continuous data retention capability without refresh operation with a low standby current of 1.14 pA. In addition, a memory array operation scheme of 3-T TRAM is proposed to address array disturbance issues. The presented array operation scheme can efficiently minimize program, erase and read disturbances on unselected cells by adjusting gate-cathode voltage. The standby voltage turns out to be beneficial to improve retention characteristics: over 10 s. With the proposed memory array operation, 3-T TRAM can provide excellent data retention characteristics and high-density memory configurations comparable with or surpass conventional dynamic random-access memory (DRAM) technology.

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