Memory Element Based on Peroxide Molecule

2018 ◽  
Vol 10 (1) ◽  
pp. 01026-1-01026-6
Author(s):  
P. O. Kondratenko ◽  
◽  
Yu. M. Lopatkin ◽  
A. G. Malashenko ◽  
T. M. Sakun ◽  
...  
Sensors ◽  
2021 ◽  
Vol 21 (7) ◽  
pp. 2506
Author(s):  
Nguyen Hoai Ngo ◽  
Kazuhiro Shimonomura ◽  
Taeko Ando ◽  
Takayoshi Shimura ◽  
Heiji Watanabe ◽  
...  

A burst image sensor named Hanabi, meaning fireworks in Japanese, includes a branching CCD and multiple CMOS readout circuits. The sensor is backside-illuminated with a light/charge guide pipe to minimize the temporal resolution by suppressing the horizontal motion of signal carriers. On the front side, the pixel has a guide gate at the center, branching to six first-branching gates, each bifurcating to second-branching gates, and finally connected to 12 (=6×2) floating diffusions. The signals are either read out after an image capture operation to replay 12 to 48 consecutive images, or continuously transferred to a memory chip stacked on the front side of the sensor chip and converted to digital signals. A CCD burst image sensor enables a noiseless signal transfer from a photodiode to the in-situ storage even at very high frame rates. However, the pixel count conflicts with the frame count due to the large pixel size for the relatively large in-pixel CCD memory elements. A CMOS burst image sensor can use small trench-type capacitors for memory elements, instead of CCD channels. However, the transfer noise from a floating diffusion to the memory element increases in proportion to the square root of the frame rate. The Hanabi chip overcomes the compromise between these pros and cons.


2020 ◽  
Vol 8 (5) ◽  
pp. 1567-1570 ◽  
Author(s):  
Mikhail Suyetin ◽  
Thomas Heine

C60−@Zn-MOF-74 operated by an electric field exhibits a combined high switching speed of 27 GB s−1 and a high memory element density of 106 Tb per inch2.


2015 ◽  
Vol 2015 ◽  
pp. 1-4
Author(s):  
Wei Zhang ◽  
Biyun L. Jackson ◽  
Ke Sun ◽  
Jae Young Lee ◽  
Shyh-Jer Huang ◽  
...  

The scalability of In2Se3, one of the phase change materials, is investigated. By depositing the material onto a nanopatterned substrate, individual In2Se3nanoclusters are confined in the nanosize pits with well-defined shape and dimension permitting the systematic study of the ultimate scaling limit of its use as a phase change memory element. In2Se3of progressively smaller volume is heated inside a transmission electron microscope operating in diffraction mode. The volume at which the amorphous-crystalline transition can no longer be observed is taken as the ultimate scaling limit, which is approximately 5 nm3for In2Se3. The physics for the existence of scaling limit is discussed. Using phase change memory elements in memory hierarchy is believed to reduce its energy consumption because they consume zero leakage power in memory cells. Therefore, the phase change memory applications are of great importance in terms of energy saving.


Author(s):  
R. Rusinek ◽  
M. Szymanski ◽  
J. Warminski

The analysis of the shape memory prosthesis (SMP) of the middle ear is presented in this paper. The shape memory prosthesis permits the adjustment of its length to individual patient needs, but sometimes the prosthesis cannot be properly fixed to the stapes. In this case, the impact between the prosthesis and stapes is important. Therefore, the reconstructed middle ear is modeled as a two degree-of-freedom system with a nonlinear shape memory element and soft impact to represent its behavior when the prosthesis is not properly placed or fixed. The properties of the shape memory prosthesis, in the form of a helical spring, are represented by a polynomial function. The system exhibits advisable periodic and undesirable aperiodic and irregular behavior depending on the excitation amplitude, the frequency, and the prosthesis length. The prosthesis length can change, resulting in a modification of the distance between the prosthesis and the stapes. The results of this study provide an answer in terms of how the prosthesis length, which produces the ossicular chain tension, influences the system dynamics and its implication in medical practice.


Author(s):  
Chaudhry Indra Kumar

The energy-efficient circuits, though important in IoT and biomedical applications, are vulnerable to soft errors due to their low voltages and small node capacitances. This paper presents an energy-efficient low-area double-node-upset-hardened latch (EEDHL). The proposed latch enhances the radiation hardness by employing a restorer circuit based on a Muller C-element and a memory element. The post-layout simulations show that the EEDHL improves the area–energy–delay product (AEDP) by [Formula: see text]80% compared to the newly reported double-node-upset-resilient latch (DNURL) in STMicroelectronics 65-nm CMOS technology. Synopsys TCAD mixed-mode simulations in 32-nm CMOS technology framework are also used to validate the proposed DNU-hardened latch. The proposed EEDHL effectively mitigates the DNU at the strike with a linear energy transfer (LET) equal to 160[Formula: see text][Formula: see text]/mg in 32-nm CMOS technology.


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