On-Chip Antennas in SiGe BiCMOS Technology: Challenges, State of the Art and Future Directions

2018 ◽  
Author(s):  
Herman Jalli Ng ◽  
Ruoyu Wang ◽  
Dietmar Kissinger
Keyword(s):  
State Of The Art ◽  
Future Directions ◽  
Bicmos Technology ◽  
Sige Bicmos ◽  
On Chip

Analysis and Design of On-Chip RF Interconnect Line for Wideband True-Time Delay Line Application

2021 ◽  
pp. 2150146
Author(s):  
Yang Chen ◽  
Zhaoyang Qiu ◽  
Xiaofei Di ◽  
Xianqing Chen ◽  
Yu-Dong Zhang
Keyword(s):  
Time Delay ◽  
Delay Line ◽  
Delay Model ◽  
Analysis And Design ◽  
True Time Delay ◽  
Bicmos Technology ◽  
Sige Bicmos ◽  
Relative Delay ◽  
True Time ◽  
On Chip

This paper presents the analytical resistance–capacitance–inductance–conductance (RLCG) model of the on-chip interconnect line (IL) based on its structure, and the proposed model can be used to design IL and analyze the delay characteristics. Using electromagnetic (EM) simulation, the relations between the inductance, quality factor and the width, length of IL are obtained, which verifies the proposed RLCG model of IL. The delay model of IL is derived and verified with respect to the effects of the [Formula: see text] and [Formula: see text] by simulation, which can provide the benefit for the true-time delay line (TTDL) design using IL. This work proposes the experiments on the delay characteristics of 3-bit TTDL with IL based on 0.13[Formula: see text][Formula: see text]m SiGe BiCMOS technology. The group delay and transient delay of the TTDL are measured, which exhibits a maximal relative delay of 35 ps with an average of 5 ps delay resolution over a frequency range of 14–34[Formula: see text]GHz. The results are consistent with the delay analysis based on the proposed IL model.

80-GHz-band low-power sub-harmonic mixer IC with a bottom-LO-configuration in 130-nm SiGe BiCMOS

2016 ◽  
Vol 8 (4-5) ◽  
pp. 703-712
Author(s):  
Xin Yang ◽  
Xiao Xu ◽  
Takayuki Shibata ◽  
Toshihiko Yoshimasu
Keyword(s):  
Supply Voltage ◽  
Current Source ◽  
Conversion Gain ◽  
Power Requirement ◽  
Harmonic Mixer ◽  
W Band ◽  
Bicmos Technology ◽  
Sige Bicmos ◽  
On Chip ◽  
Marchand Balun

In this paper, a W-band (80 GHz) sub-harmonic mixer (SHM) IC is designed, fabricated and measured in 130-nm SiGe BiCMOS technology. The presented SHM IC makes use of a common emitter common collector transistor pair structure with a bottom-LO-configuration to decrease the LO power requirement and a tail current source to flatten the conversion gain. On-chip Marchand balun is designed for W-band on-wafer measurements. The SHM IC presented in this paper has exhibited a conversion gain of 3.9 dB at 80 GHz RF signal with an LO power of only −7 dBm at 39.5 GHz. The mixer core consumes only 0.68 mA at a supply voltage of 3.3 V.

Low-power 8-bit 5-GS/s digital-to-analog converter for multi-gigabit wireless transceivers

2012 ◽  
Vol 4 (3) ◽  
pp. 275-282 ◽  
Author(s):  
Behnam Sedighi ◽  
Mahdi Khafaji ◽  
Johann Christoph Scheytt
Keyword(s):  
Low Power ◽  
High Speed ◽  
Wireless Transceivers ◽  
Digital To Analog Converter ◽  
Bicmos Technology ◽  
Analog Converter ◽  
Sige Bicmos ◽  
Digital To Analog ◽  
On Chip ◽  
Binary Weighted

We present a method to realize a low-power and high-speed digital-to-analog converter (DAC) for system-on-chip applications. The new method is a combination of binary-weighted current cells and R-2R ladder and is specially suited for modern BiCMOS technologies. A prototype 5 GS/s DAC is implemented in 0.13 μm SiGe BiCMOS technology. The DAC dissipates 26 mW and provides an SFDR higher than 48 dB for output frequencies up to 1 GHz.

scholarly journals Design of Differential Variable-Gain Transimpedance Amplifier in 0.18 µm SiGe BiCMOS

Electronics ◽  
2020 ◽  
Vol 9 (7) ◽  
pp. 1058
Author(s):  
Samuel B.S. Lee ◽  
Hang Liu ◽  
Kiat Seng Yeo ◽  
Jer-Ming Chen ◽  
Xiaopeng Yu
Keyword(s):  
Dynamic Range ◽  
Third Order ◽  
Transimpedance Amplifiers ◽  
Variable Gain ◽  
Gain Variation ◽  
Bicmos Technology ◽  
Capacitive Load ◽  
Sige Bicmos ◽  
Amplifier Stage ◽  
On Chip

This paper presents two new inductorless differential variable-gain transimpedance amplifiers (DVGTIA) with voltage bias controlled variable gain designed in TowerJazz’s 0.18 µm SiGe BiCMOS technology (using CMOS transistors only). Both consist of a modified differential cross-coupled regulated cascode preamplifier stage and a cascaded amplifier stage with bias-controlled gain-variation and third-order interleaving feedback. The designs have wide measured transimpedance gain ranges of 24.5–60.6 dBΩ and 27.8–62.8 dBΩ with bandwidth above 6.42 GHz and 5.22 GHz for DVGTIA designs 1 and 2 respectively. The core power consumptions are 30.7 mW and 27.5 mW from a 1.8 V supply and the input referred noise currents are 10.3 pA/√Hz and 21.7 pA/√Hz. The DVGTIA designs 1 and 2 have a dynamic range of 40.4 µA to 3 mA and 76.8 µA to 2.7 mA making both suitable for real photodetectors with an on-chip photodetector capacitive load of 250 fF. Both designs are compact with a core area of 100 µm × 85 µm.

D-Band Transmitter/Receiver Chipset with End-Fire On-chip Antennas Using 0.13-μm SiGe BiCMOS Technology

2020 ◽  
Vol 41 (3) ◽  
pp. 322-339
Author(s):  
Chunhong Chen ◽  
Xiaodong Deng ◽  
Yihu Li ◽  
Wen Wu ◽  
Yong-Zhong Xiong
Keyword(s):  
Bicmos Technology ◽  
Sige Bicmos ◽  
On Chip

122 GHz single-chip dual-channel SMD radar sensor with on-chip antennas for distance and angle measurements

2015 ◽  
Vol 7 (3-4) ◽  
pp. 407-414 ◽  
Author(s):  
Mekdes G. Girma ◽  
Markus Gonser ◽  
Andreas Frischen ◽  
Jürgen Hasch ◽  
Yaoming Sun ◽  
...  
Keyword(s):  
Building Blocks ◽  
Single Chip ◽  
Fully Integrated ◽  
Dual Channel ◽  
Angle Measurements ◽  
Bicmos Technology ◽  
Measurement Results ◽  
Sige Bicmos ◽  
On Chip ◽  
Digital Processor

This paper describes the design considerations, integration issues, packaging, and experimental performance of recently developed D-Band dual-channel transceiver with on-chip antennas fabricated in a SiGe-BiCMOS technology. The design comprises a fully integrated transceiver circuit with quasi-monostatic architecture that operates between 114 and 124 GHz. All analog building blocks are controllable via a serial peripheral interface to reduce the number of connections and facilitate the communication between digital processor and analog building blocks. The two electromagnetically coupled patch antennas are placed on the top of the die with 8.6 dBi gain and have a simulated efficiency of 60%. The chip consumes 450 mW and is wire-bonded into an open-lid 5 × 5 mm2quad-flat no-leads package. Measurement results for the estimation of range, and azimuth angle in single object situation are presented.

Sign in / Sign up

Export Citation Format

Share Document