scholarly journals A 65 nm Duplex Transconductance Path Up-Conversion Mixer for 24 GHz Automotive Short-Range Radar Sensor Applications

Sensors ◽  
2022 ◽  
Vol 22 (2) ◽  
pp. 594
Author(s):  
Tahesin Samira Delwar ◽  
Abrar Siddique ◽  
Manas Ranjan Biswal ◽  
Prangyadarsini Behera ◽  
Yeji Choi ◽  
...  
Keyword(s):  
Power Dissipation ◽  
Short Range ◽  
Noise Figure ◽  
Supply Voltage ◽  
Common Source ◽  
Cmos Process ◽  
Radar Sensor ◽  
Sensor Applications ◽  
The Common ◽  
24 Ghz

A 24 GHz highly-linear upconversion mixer, based on a duplex transconductance path (DTP), is proposed for automotive short-range radar sensor applications using the 65-nm CMOS process. A mixer with an enhanced transconductance stage consisting of a DTP is presented to improve linearity. The main transconductance path (MTP) of the DTP includes a common source (CS) amplifier, while the secondary transconductance path (STP) of the DTP is implemented as an improved cross-quad transconductor (ICQT). Two inductors with a bypass capacitor are connected at the common nodes of the transconductance stage and switching stage of the mixer, which acts as a resonator and helps to improve the gain and isolation of the designed mixer. According to the measured results, at 24 GHz the proposed mixer shows that the linearity of output 1-dB compression point (OP1dB) is 3.9 dBm. And the input 1-dB compression point (IP1dB) is 0.9 dBm. Moreover, a maximum conversion gain (CG) of 2.49 dB and a noise figure (NF) of 3.9 dB is achieved in the designed mixer. When the supply voltage is 1.2 V, the power dissipation of the mixer is 3.24 mW. The mixer chip occupies an area of 0.42 mm2.

scholarly journals Development of Low-Noise Small-Area 24 GHz CMOS Radar Sensor

2016 ◽  
Vol 2016 ◽  
pp. 1-12
Author(s):  
Min Yoon ◽  
Jee-Youl Ryu
Keyword(s):  
Low Power ◽  
Power Dissipation ◽  
Small Area ◽  
Noise Figure ◽  
Low Noise ◽  
Cmos Process ◽  
Radar Sensor ◽  
Low Power Dissipation ◽  
Chip Size ◽  
24 Ghz

We present a low-noise small-area 24 GHz CMOS radar sensor for automotive collision avoidance. This sensor is based on direct-conversion pulsed-radar architecture. The proposed circuit is implemented using TSMC 0.13 μm RF (radio frequency) CMOS (fT/fmax=120/140 GHz) technology, and it is powered by a 1.5 V supply. This circuit uses transmission lines to reduce total chip size instead of real bulky inductors for input and output impedance matching. The layout techniques for RF are used to reduce parasitic capacitance at the band of 24 GHz. The proposed sensor has low cost and low power dissipation since it is realized using CMOS process. The proposed sensor showed the lowest noise figure of 2.9 dB and the highest conversion gain of 40.2 dB as compared to recently reported research results. It also showed small chip size of 0.56 mm2, low power dissipation of 39.5 mW, and wide operating temperature range of −40 to +125°C.

scholarly journals Design of Common-gate with Common-source Active Balun for WiMAX Receiver Front-end

2019 ◽  
pp. 1-9
Author(s):  
Frederick Ray I. Gomez ◽  
Maria Theresa G. De Leon ◽  
John Richard E. Hizon
Keyword(s):  
Phase Difference ◽  
Noise Figure ◽  
Supply Voltage ◽  
Complementary Metal Oxide Semiconductor ◽  
Oxide Semiconductor ◽  
Common Source ◽  
Cmos Process ◽  
Common Gate ◽  
Active Balun ◽  
The Common

This paper presents a design and simulation study of a common-gate with common-source active balun circuit implemented in a standard 90-nm complementary metal-oxide semiconductor (CMOS) process.  The active balun design is intended for worldwide interoperability for microwave access (WiMAX) application, with operating frequency of 5.8 GHz and supply voltage of 1 V.  Measurements are taken for parameters namely gain difference, phase difference, and noise figure.  The common-source active balun design achieved a minimal gain difference of  0.04 dB, phase difference of 180 ± 1.5 degrees, and noise figure of 8.76 dB, which are comparable to past active balun designs and researches.  The design eventually achieved a low power consumption of 4.45 mW.

A 1.4mW 900MHz LNA with Noise-Canceling Technique in 130nm CMOS Process

2017 ◽  
Vol 27 (01) ◽  
pp. 1850003 ◽  
Author(s):  
Shaomin Huang ◽  
Zhongpan Yang ◽  
Chao Hua
Keyword(s):  
Power Dissipation ◽  
Noise Figure ◽  
Supply Voltage ◽  
Low Noise ◽  
Common Source ◽  
Cmos Process ◽  
Measurement Results ◽  
Common Gate ◽  
Noise Amplifier ◽  
Noise Canceling

A noise-canceling low noise amplifier (LNA) structure is proposed in this paper. The LNA works in the 900[Formula: see text]MHz ISM band. The techniques of noise canceling and current-reusing are proposed to improve the noise performance and reduce the power dissipation. The noise cancellation schema is realized by mutually canceling the noise currents of the common-source and common-gate amplifiers. A prototype of the LNA is designed and fabricated in a standard 130[Formula: see text]nm CMOS process. Measurement results under a 1.2[Formula: see text]V supply voltage show that the proposed LNA achieves a voltage gain of 18[Formula: see text]dB and a noise figure of 2[Formula: see text]dB. The whole circuit only consumes a power dissipation of 1.4[Formula: see text]mW.

scholarly journals Design and Simulation Study of Active Baluns Circuits for WiMAX Applications

2019 ◽  
Vol 7 (1) ◽  
Author(s):  
Frederick Ray I. Gomez ◽  
John Richard E. Hizon ◽  
Maria Theresa G. De Leon
Keyword(s):  
Phase Difference ◽  
Simulation Study ◽  
Noise Figure ◽  
Supply Voltage ◽  
Complementary Metal Oxide Semiconductor ◽  
Oxide Semiconductor ◽  
Common Source ◽  
Cmos Process ◽  
Common Gate ◽  
Active Balun

The paper presents a design and simulation study of three active balun circuits implemented in a standard 90nm Complementary Metal-Oxide Semiconductor (CMOS) process namely: (1) common-source/drain active balun; (2) common-gate with common-source active balun; and (3) differential active balun.  The active balun designs are intended for Worldwide Interoperability for Microwave Access (WiMAX) applications operating at frequency 5.8GHz and with supply voltage of 1V.  Measurements are taken for parameters such as gain difference, phase difference, and noise figure.  All designs achieved gain difference of less than 0.23dB, phase difference of 180° ± 7.1°, and noise figure of 7.2–9.85dB, which are comparable to previous designs and researches.  Low power consumption attained at the most 4.45mW.

High-Swing, High-Resolution, Low-Power, Low-Area Voltage-Mode LTA/WTA Circuits

2015 ◽  
Vol 24 (07) ◽  
pp. 1550103 ◽  
Author(s):  
Mohammad Soleimani ◽  
Siroos Toofan ◽  
Mostafa Yargholi
Keyword(s):  
High Resolution ◽  
Low Power ◽  
Power Dissipation ◽  
Supply Voltage ◽  
Rank Order ◽  
Active Area ◽  
Total Power ◽  
Common Source ◽  
Cmos Process ◽  
Process Technology

In this paper, a general architecture for analog implementation of loser/winner-take-all (LTA/WTA) and other rank order circuits is presented. This architecture is composed of a differential amplifier with merged n-inputs and a merged common-source with active load (MCSAL) circuit to choose the desired input. The advantages of the proposed structure are simplicity, very high resolution, very low supply voltage requirements, very low output resistor, low power dissipation, low active area and simple expansion for multiple inputs by adding only three transistors for each extra input. The post-layout simulation results of proposed circuits are presented by HSPICE software in 0.35-μm CMOS process technology. The total power dissipation of proposed circuits is about 110-μW. Also, the total active area is about 550-μm2 for five-input proposed circuits, and would be negligibly increased for each extra input.

scholarly journals Design of Common-Source/Drain Active Balun Using 90nm CMOS Technology

2019 ◽  
pp. 1-9
Author(s):  
Frederick Ray I. Gomez ◽  
Maria Theresa G. De Leon ◽  
John Richard E. Hizon
Keyword(s):  
Phase Difference ◽  
Noise Figure ◽  
Supply Voltage ◽  
Complementary Metal Oxide Semiconductor ◽  
Cmos Technology ◽  
Metal Oxide Semiconductor ◽  
Oxide Semiconductor ◽  
Common Source ◽  
Active Balun ◽  
The Common

This research paper presents a design and study of a common-source/drain active balun circuit implemented in a standard 90-nm complementary metal-oxide semiconductor (CMOS) technology.  The active balun design is intended for worldwide interoperability for microwave access (WiMAX) application, with operating frequency of 5.8GHz and supply voltage of 1V.  Measurements are taken for parameters namely gain difference, phase difference, and noise figure.  The common-source active balun design achieved a minimal gain difference of 0.016dB, phase difference of 180° ± 7.1°, and noise figure of 7.42-9.85dB, which are comparable to past active balun designs and researches.  The design eventually achieved a low power consumption of 2.56mW.

scholarly journals VERY LARGE SCALE INTEGRATION TINY CHIP WITH NANOPOWER SENSOR APPLICATIONS

2012 ◽  
pp. 116-120
Author(s):  
K.JAYA SWAROOP ◽  
M.I. SUDHARAYAPPA ◽  
CH. JAYAPRAKASH ◽  
V.SURENDRA BABU
Keyword(s):  
Power Consumption ◽  
Power Dissipation ◽  
Large Scale ◽  
Supply Voltage ◽  
Vlsi Design ◽  
Electrical Characterization ◽  
Cmos Process ◽  
Process Technology ◽  
Voltage Range ◽  
Sensor Applications

Semiconductor devices have rapidly advanced over the past years increasing switching(on and off) speed and density of the device, causing an increase in power consumption and power dissipation; accordingly, the issues have been considered and improved . In CMOS 0.5μm process, the designed VLSI mirror-amplifier had power dissipation of 8.41 milliwatts. This technique is changed in this paper. The biasing is done in two steps proved to be correct procedure to improve overall power consumption. Source voltage was considered as 3V for the MOSIS process technology. Layout ,simulation and electrical characterization of the design were carried out by MENTOR GRAPHICS tool and CAD tools were used for the design Holding the scaling and process unchanged at 0.5μm as the previous design, the new VLSI design had power dissipation of 4.39 nanowatts in second step by reducing the dynamic loss. Multi-die chip placement is done for fabrication. More advanced 0.35um CMOS process is used for low threshold voltage and enhanced supply voltage range. This paper presents details of the key research works, results, completed chip layout and applications of the chip.

scholarly journals Design and Analysis of a Novel 24 GHz Up-Conversion Mixer with Improved Derivative Super-Position Linearizer Technique for 5G Applications

Sensors ◽  
2021 ◽  
Vol 21 (18) ◽  
pp. 6118
Author(s):  
Abrar Siddique ◽  
Tahesin Samira Delwar ◽  
Prangyadarsini Behera ◽  
Manas Ranjan Biswal ◽  
Amir Haider ◽  
...  
Keyword(s):  
Noise Figure ◽  
High Gain ◽  
Common Source ◽  
Cmos Process ◽  
Third Order ◽  
Linear Coefficient ◽  
Chip Area ◽  
The Third ◽  
Fifth Generation ◽  
24 Ghz

A 24 GHz high linear, high-gain up-conversion mixer is realized for fifth-generation (5G) applications in the 65 nm CMOS process. The mixer’s linearity is increased by applying an Improved Derivative Super-Position (I-DS) technique cascaded between the mixer’s transconductance and switching stage. The high gain and stability of amplifiers in the transconductance stage of the mixer are achieved using novel tunable capacitive cross-coupled common source (TCC-CS) transistors. Using the I-DS, the third-order non-linear coefficient of current is closed to zero, enhancing the linearity. Additionally, a TCC-CS, which is realized by varactors, neutralizes the gate-to-drain parasitic capacitance (Cgd) of transistors in the transconductance stage of the mixer and contributes to the improvement of the gain and stability of the mixer. The measured 1 dB compression point OP1dB of the designed mixer is 4.1 dBm and IP1dB is 0.67 dBm at 24 GHz. The conversion gain of 4.1 dB at 24 GHz and 3.2 ± 0.9 dB, from 20 to 30 GHz is achieved in the designed mixer. Furthermore, a noise figure of 3.8 dB is noted at 24 GHz. The power consumption of the mixer is 4.9 mW at 1.2 V, while the chip area of the designed mixer is 0.4 mm2.

scholarly journals An 18.8–33.9 GHz, 2.26 mW Current-Reuse Injection-Locked Frequency Divider for Radar Sensor Applications

Sensors ◽  
2021 ◽  
Vol 21 (7) ◽  
pp. 2551
Author(s):  
Kwang-Il Oh ◽  
Goo-Han Ko ◽  
Jeong-Geun Kim ◽  
Donghyun Baek
Keyword(s):  
Supply Voltage ◽  
Cmos Technology ◽  
Frequency Divider ◽  
Oxide Semiconductor ◽  
Center Frequency ◽  
Radar Sensor ◽  
Frequency Locking ◽  
Current Reuse ◽  
Sensor Applications ◽  
Locking Range

An 18.8–33.9 GHz, 2.26 mW current-reuse (CR) injection-locked frequency divider (ILFD) for radar sensor applications is presented in this paper. A fourth-order resonator is designed using a transformer with a distributed inductor for wideband operating of the ILFD. The CR core is employed to reduce the power consumption compared to conventional cross-coupled pair ILFDs. The targeted input center frequency is 24 GHz for radar application. The self-oscillated frequency of the proposed CR-ILFD is 14.08 GHz. The input frequency locking range is from 18.8 to 33.8 GHz (57%) at an injection power of 0 dBm without a capacitor bank or varactors. The proposed CR-ILFD consumes 2.26 mW of power from a 1 V supply voltage. The entire die size is 0.75 mm × 0.45 mm. This CR-ILFD is implemented in a 65 nm complementary metal-oxide semiconductor (CMOS) technology.

scholarly journals RF Transceiver for the Multi-Mode Radar Applications

Sensors ◽  
2021 ◽  
Vol 21 (5) ◽  
pp. 1563
Author(s):  
Jae Kwon Ha ◽  
Chang Kyun Noh ◽  
Jin Seop Lee ◽  
Ho Jin Kang ◽  
Yu Min Kim ◽  
...  
Keyword(s):  
Long Range ◽  
Integrated Circuit ◽  
Flicker Noise ◽  
Noise Figure ◽  
Supply Voltage ◽  
Doppler Frequency ◽  
Cmos Process ◽  
Rf Transceiver ◽  
Dc Offset ◽  
Multi Mode

In this work, a multi-mode radar transceiver supporting pulse, FMCW and CW modes was designed as an integrated circuit. The radars mainly detect the targets move by using the Doppler frequency which is significantly affected by flicker noise of the receiver from several Hz to several kHz. Due to this flicker noise, the long-range detection performance of the radars is greatly reduced, and the accuracy of range to the target and velocity is also deteriorated. Therefore, we propose a transmitter that suppresses LO leakage in consideration of long-range detection, target distance, velocity, and noise figure. We also propose a receiver structure that suppresses DC offset due to image signal and LO leakage. The design was conducted with TSMC 65 nm CMOS process, and the designed and fabricated circuit consumes a current of 265 mA at 1.2 V supply voltage. The proposed transmitter confirms the LO leakage suppression of 37 dB at 24 GHz. The proposed receiver improves the noise figure by about 20 dB at 100 Hz by applying a double conversion architecture and an image rejection, and it illustrates a DC rejection of 30 dB. Afterwards, the operation of the pulse, FMCW, and CW modes of the designed radar in integrated circuit was confirmed through experiment using a test PCB.

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