Review: Static and Dynamic Analysis Methods for Multi-Branch Biasing Circuits

2018 ◽  
Vol 27 (13) ◽  
pp. 1830008
Author(s):  
Jin Wu ◽  
Pengfei Dai ◽  
Jie Peng ◽  
Lixia Zheng ◽  
Weifeng Sun
Keyword(s):  
Feedback Loop ◽  
Supply Voltage ◽  
Complementary Metal Oxide Semiconductor ◽  
Oxide Semiconductor ◽  
Critical Parameters ◽  
Cmos Process ◽  
Stable Equilibrium Point ◽  
Static And Dynamic Analysis ◽  
Text Structures ◽  
Different Types

The fundamental theories and primary structures for the multi-branch self-biasing circuits are reviewed in this paper. First, the [Formula: see text]/[Formula: see text] and [Formula: see text]/[Formula: see text] structures illustrating the static current definition mechanism are presented, including the conditions of starting up and entering into a stable equilibrium point. Then, the AC method based on the loop gain evaluation is utilized to analyze different types of circuits. On this basis, the laws which can couple the branches of self-biasing circuits to construct a suitable close feedback loop are summarized. By adopting Taiwan Semiconductor Manufacturing Company (TSMC)’s 0.18[Formula: see text][Formula: see text]m complementary metal–oxide–semiconductor (CMOS) process with 1.8[Formula: see text][Formula: see text] supply voltage, nearly all the circuits mentioned in the paper are simulated in the same branch current condition, which is close to the corresponding calculated results. Therefore, the methods summarized in this paper can be utilized for distinguishing, constructing, and optimizing critical parameters for various structures of the self-biasing circuits.

scholarly journals DIGITAL CONTROLLED OSCILLATOR (DCO) FOR ALL DIGITAL PHASE-LOCKED LOOP (ADPLL) – A REVIEW

2019 ◽  
Vol 82 (1) ◽  
Author(s):  
Florence Choong ◽  
Mamun Ibne Reaz ◽  
Mohamad Ibrahim Kamaruzzaman ◽  
Md. Torikul Islam Badal ◽  
Araf Farayez ◽  
...  
Keyword(s):  
Supply Voltage ◽  
Complementary Metal Oxide Semiconductor ◽  
Phase Locked Loop ◽  
Cmos Technology ◽  
Oxide Semiconductor ◽  
Cmos Process ◽  
Process Technology ◽  
Chip Area ◽  
Digital Phase ◽  
Low Power Dissipation

Digital controlled oscillator (DCO) is becoming an attractive replacement over the voltage control oscillator (VCO) with the advances of digital intensive research on all-digital phase locked-loop (ADPLL) in complementary metal-oxide semiconductor (CMOS) process technology. This paper presents a review of various CMOS DCO schemes implemented in ADPLL and relationship between the DCO parameters with ADPLL performance. The DCO architecture evaluated through its power consumption, speed, chip area, frequency range, supply voltage, portability and resolution. It can be concluded that even though there are various schemes of DCO that have been implemented for ADPLL, the selection of the DCO is frequently based on the ADPLL applications and the complexity of the scheme. The demand for the low power dissipation and high resolution DCO in CMOS technology shall remain a challenging and active area of research for years to come. Thus, this review shall work as a guideline for the researchers who wish to work on all digital PLL.

scholarly journals Design and Simulation Study of Active Baluns Circuits for WiMAX Applications

2019 ◽  
Vol 7 (1) ◽  
Author(s):  
Frederick Ray I. Gomez ◽  
John Richard E. Hizon ◽  
Maria Theresa G. De Leon
Keyword(s):  
Phase Difference ◽  
Simulation Study ◽  
Noise Figure ◽  
Supply Voltage ◽  
Complementary Metal Oxide Semiconductor ◽  
Oxide Semiconductor ◽  
Common Source ◽  
Cmos Process ◽  
Common Gate ◽  
Active Balun

The paper presents a design and simulation study of three active balun circuits implemented in a standard 90nm Complementary Metal-Oxide Semiconductor (CMOS) process namely: (1) common-source/drain active balun; (2) common-gate with common-source active balun; and (3) differential active balun.  The active balun designs are intended for Worldwide Interoperability for Microwave Access (WiMAX) applications operating at frequency 5.8GHz and with supply voltage of 1V.  Measurements are taken for parameters such as gain difference, phase difference, and noise figure.  All designs achieved gain difference of less than 0.23dB, phase difference of 180° ± 7.1°, and noise figure of 7.2–9.85dB, which are comparable to previous designs and researches.  Low power consumption attained at the most 4.45mW.

scholarly journals Design of Common-gate with Common-source Active Balun for WiMAX Receiver Front-end

2019 ◽  
pp. 1-9
Author(s):  
Frederick Ray I. Gomez ◽  
Maria Theresa G. De Leon ◽  
John Richard E. Hizon
Keyword(s):  
Phase Difference ◽  
Noise Figure ◽  
Supply Voltage ◽  
Complementary Metal Oxide Semiconductor ◽  
Oxide Semiconductor ◽  
Common Source ◽  
Cmos Process ◽  
Common Gate ◽  
Active Balun ◽  
The Common

This paper presents a design and simulation study of a common-gate with common-source active balun circuit implemented in a standard 90-nm complementary metal-oxide semiconductor (CMOS) process.  The active balun design is intended for worldwide interoperability for microwave access (WiMAX) application, with operating frequency of 5.8 GHz and supply voltage of 1 V.  Measurements are taken for parameters namely gain difference, phase difference, and noise figure.  The common-source active balun design achieved a minimal gain difference of  0.04 dB, phase difference of 180 ± 1.5 degrees, and noise figure of 8.76 dB, which are comparable to past active balun designs and researches.  The design eventually achieved a low power consumption of 4.45 mW.

scholarly journals Differential Active Balun Design for WiMAX Applications

2019 ◽  
pp. 1-8
Author(s):  
Frederick Ray I. Gomez ◽  
John Richard E. Hizon ◽  
Maria Theresa G. De Leon
Keyword(s):  
Phase Difference ◽  
Simulation Study ◽  
Noise Figure ◽  
Supply Voltage ◽  
Complementary Metal Oxide Semiconductor ◽  
Metal Oxide Semiconductor ◽  
Oxide Semiconductor ◽  
Low Power Consumption ◽  
Cmos Process ◽  
Active Balun

The paper presents a design and simulation study of a differential active balun circuit implemented in a standard 90 nm complementary metal-oxide semiconductor (CMOS) process.  The active balun design is intended for Worldwide Interoperability for Microwave Access (WiMAX) applications operating at frequency 5.8 GHz and with supply voltage of 1V.  Measurements are taken for parameters such as gain difference, phase difference, and noise figure.  The differential active balun design achieved gain difference of less than 0.23 dB, phase difference of 180° ± 3.4°, and noise figure of 9.78 dB, which are comparable to past active balun designs and researches.  Lastly, the design achieved a low power consumption of 3.6 mW.

scholarly journals Phase Change Metasurfaces by Continuous or Quasi-Continuous Atoms for Active Optoelectronic Integration

Materials ◽  
2021 ◽  
Vol 14 (5) ◽  
pp. 1272
Author(s):  
Zhihua Fan ◽  
Qinling Deng ◽  
Xiaoyu Ma ◽  
Shaolin Zhou
Keyword(s):  
Phase Change ◽  
Phase Change Materials ◽  
Complementary Metal Oxide Semiconductor ◽  
Photonic Devices ◽  
Oxide Semiconductor ◽  
Cmos Process ◽  
Nanophotonic Devices ◽  
Optoelectronic Integration ◽  
Hybrid Devices ◽  
Micro Electromechanical System

In recent decades, metasurfaces have emerged as an exotic and appealing group of nanophotonic devices for versatile wave regulation with deep subwavelength thickness facilitating compact integration. However, the ability to dynamically control the wave–matter interaction with external stimulus is highly desirable especially in such scenarios as integrated photonics and optoelectronics, since their performance in amplitude and phase control settle down once manufactured. Currently, available routes to construct active photonic devices include micro-electromechanical system (MEMS), semiconductors, liquid crystal, and phase change materials (PCMs)-integrated hybrid devices, etc. For the sake of compact integration and good compatibility with the mainstream complementary metal oxide semiconductor (CMOS) process for nanofabrication and device integration, the PCMs-based scheme stands out as a viable and promising candidate. Therefore, this review focuses on recent progresses on phase change metasurfaces with dynamic wave control (amplitude and phase or wavefront), and especially outlines those with continuous or quasi-continuous atoms in favor of optoelectronic integration.

scholarly journals Universal Filter Based on Compact CMOS Structure of VDDDA

Sensors ◽  
2021 ◽  
Vol 21 (5) ◽  
pp. 1683
Author(s):  
Winai Jaikla ◽  
Fabian Khateb ◽  
Tomasz Kulej ◽  
Koson Pitaksuttayaprot
Keyword(s):  
Metal Oxide ◽  
Dynamic Range ◽  
Complementary Metal Oxide Semiconductor ◽  
Metal Oxide Semiconductor ◽  
Experimental Results ◽  
Oxide Semiconductor ◽  
Cmos Process ◽  
Voltage Gain ◽  
Universal Filter ◽  
Mos Transistor

This paper proposes the simulated and experimental results of a universal filter using the voltage differencing differential difference amplifier (VDDDA). Unlike the previous complementary metal oxide semiconductor (CMOS) structures of VDDDA that is present in the literature, the present one is compact and simple, owing to the employment of the multiple-input metal oxide semiconductor (MOS) transistor technique. The presented filter employs two VDDDAs, one resistor and two grounded capacitors, and it offers low-pass: LP, band-pass: BP, band-reject: BR, high-pass: HP and all-pass: AP responses with a unity passband voltage gain. The proposed universal voltage mode filter has high input impedances and low output impedance. The natural frequency and bandwidth are orthogonally controlled by using separated transconductance without affecting the passband voltage gain. For a BP filter, the root mean square (RMS) of the equivalent output noise is 46 µV, and the third intermodulation distortion (IMD3) is −49.5 dB for an input signal with a peak-to peak of 600 mV, which results in a dynamic range (DR) of 73.2 dB. The filter was designed and simulated in the Cadence environment using a 0.18-µm CMOS process from Taiwan semiconductor manufacturing company (TSMC). In addition, the experimental results were obtained by using the available commercial components LM13700 and AD830. The simulation results are in agreement with the experimental one that confirmed the advantages of the filter.

scholarly journals Investigation of PVT-Aware STT-MRAM Sensing Circuits for Low-VDD Scenario

Micromachines ◽  
2021 ◽  
Vol 12 (5) ◽  
pp. 551
Author(s):  
Zhongjian Bian ◽  
Xiaofeng Hong ◽  
Yanan Guo ◽  
Lirida Naviner ◽  
Wei Ge ◽  
...  
Keyword(s):  
Nonvolatile Memory ◽  
High Speed ◽  
Low Voltage ◽  
Supply Voltage ◽  
Random Access ◽  
Magnetic Tunnel Junction ◽  
Complementary Metal Oxide Semiconductor ◽  
Current Mode ◽  
Cmos Technology ◽  
Oxide Semiconductor

Spintronic based embedded magnetic random access memory (eMRAM) is becoming a foundry validated solution for the next-generation nonvolatile memory applications. The hybrid complementary metal-oxide-semiconductor (CMOS)/magnetic tunnel junction (MTJ) integration has been selected as a proper candidate for energy harvesting, area-constraint and energy-efficiency Internet of Things (IoT) systems-on-chips. Multi-VDD (low supply voltage) techniques were adopted to minimize energy dissipation in MRAM, at the cost of reduced writing/sensing speed and margin. Meanwhile, yield can be severely affected due to variations in process parameters. In this work, we conduct a thorough analysis of MRAM sensing margin and yield. We propose a current-mode sensing amplifier (CSA) named 1D high-sensing 1D margin, high 1D speed and 1D stability (HMSS-SA) with reconfigured reference path and pre-charge transistor. Process-voltage-temperature (PVT) aware analysis is performed based on an MTJ compact model and an industrial 28 nm CMOS technology, explicitly considering low-voltage (0.7 V), low tunneling magnetoresistance (TMR) (50%) and high temperature (85 °C) scenario as the worst sensing case. A case study takes a brief look at sensing circuits, which is applied to in-memory bit-wise computing. Simulation results indicate that the proposed high-sensing margin, high speed and stability sensing-sensing amplifier (HMSS-SA) achieves remarkable performance up to 2.5 GHz sensing frequency. At 0.65 V supply voltage, it can achieve 1 GHz operation frequency with only 0.3% failure rate.

Millimeter-wave dual-mode and dual-band switchable Gilbert up-conversion mixer in 65-nm CMOS process

2021 ◽  
pp. 1-5
Author(s):  
Fang Zhu ◽  
Guo Qing Luo
Keyword(s):  
Millimeter Wave ◽  
Complementary Metal Oxide Semiconductor ◽  
Local Oscillator ◽  
Metal Oxide Semiconductor ◽  
Oxide Semiconductor ◽  
Dual Band ◽  
Cmos Process ◽  
Pumping Power ◽  
Dual Mode ◽  
Dc Power

Abstract In this paper, a millimeter-wave (MMW) dual-mode and dual-band switchable Gilbert up-conversion mixer in a commercial 65-nm complementary metal oxide semiconductor (CMOS) process is presented. By simply changing the bias, the proposed CMOS Gilbert up-conversion mixer can be switched between subharmonic and fundamental operation modes for MMW dual-band applications. With a low local oscillator pumping power of 3 dBm and low dc power consumption of 6 mW, the proposed CMOS Gilbert up-conversion mixer exhibits a measured conversion gain of −0.5 ± 1.5 dB from 37 to 50 GHz and 2.5 ± 1.5 dB from 17.5 to 32 GHz for the subharmonic and fundamental modes, respectively.

scholarly journals Performance Comparison of Carry-Lookahead and Carry-Select Adders Based on Accurate and Approximate Additions

Electronics ◽  
2018 ◽  
Vol 7 (12) ◽  
pp. 369 ◽  
Author(s):  
Padmanabhan Balasubramanian ◽  
Nikos Mastorakis
Keyword(s):  
High Speed ◽  
Digital Signal ◽  
Complementary Metal Oxide Semiconductor ◽  
Performance Comparison ◽  
Oxide Semiconductor ◽  
Cmos Process ◽  
Least Significant Bit ◽  
Design Metrics ◽  
Ripple Carry Adder ◽  
Speed Performance

Addition is a fundamental operation in microprocessing and digital signal processing hardware, which is physically realized using an adder. The carry-lookahead adder (CLA) and the carry-select adder (CSLA) are two popular high-speed, low-power adder architectures. The speed performance of a CLA architecture can be improved by adopting a hybrid CLA architecture which employs a small-size ripple-carry adder (RCA) to replace a sub-CLA in the least significant bit positions. On the other hand, the power dissipation of a CSLA employing full adders and 2:1 multiplexers can be reduced by utilizing binary-to-excess-1 code (BEC) converters. In the literature, the designs of many CLAs and CSLAs were described separately. It would be useful to have a direct comparison of their performances based on the design metrics. Hence, we implemented homogeneous and hybrid CLAs, and CSLAs with and without the BEC converters by considering 32-bit accurate and approximate additions to facilitate a comparison. For the gate-level implementations, we considered a 32/28 nm complementary metal-oxide-semiconductor (CMOS) process targeting a typical-case process–voltage–temperature (PVT) specification. The results show that the hybrid CLA/RCA architecture is preferable among the CLA and CSLA architectures from the speed and power perspectives to perform accurate and approximate additions.

scholarly journals A Regulated Temperature-Insensitive High-Voltage Charge Pump in Standard CMOS Process for Micromachined Gyroscopes

Sensors ◽  
2019 ◽  
Vol 19 (19) ◽  
pp. 4149
Author(s):  
Xiang Li ◽  
Rui Li ◽  
Chunge Ju ◽  
Bo Hou ◽  
Qi Wei ◽  
...  
Keyword(s):  
Metal Oxide ◽  
High Voltage ◽  
Output Voltage ◽  
Charge Pump ◽  
Complementary Metal Oxide Semiconductor ◽  
Metal Oxide Semiconductor ◽  
Oxide Semiconductor ◽  
Cmos Process ◽  
Temperature Changes ◽  
Adjustable Range

Micromachined gyroscopes require high voltage (HV) for actuation and detection to improve its precision, but the deviation of the HV caused by temperature fluctuations will degrade the sensor’s performance. In this paper, a high-voltage temperature-insensitive charge pump is proposed. Without adopting BCD (bipolar-CMOS-DMOS) technology, the output voltage can be boosted over the breakdown voltage of n-well/substrate diode using triple-well NMOS (n-type metal-oxide-semiconductor) transistors. By controlling the pumping clock’s amplitude continuously, closed-loop regulation is realized to reduce the output voltage’s sensitivity to temperature changes. Besides, the output level is programmable linearly in a large range by changing the reference voltage. The whole circuit has been fabricated in a 0.18- μ m standard CMOS (complementary metal-oxide-semiconductor) process with a total area of 2.53 mm 2 . Measurements indicate that its output voltage has a linear adjustable range from around 13 V to 16.95 V, and temperature tests show that the maximum variations of the output voltage at − 40 ∼ 80 ∘ C are less than 1.1%.

Sign in / Sign up

Export Citation Format

Share Document