scholarly journals High-Efficiency High-Gain 2.4 GHz Class-B Power Amplifiers in 0.13 µm CMOS for Wireless Communications

2017 ◽  
Author(s):  
Tuan Anh Vu ◽  
Tuan Dinh Pham ◽  
Duong Gia Bach
Keyword(s):  
Wireless Communications ◽  
High Power ◽  
Power Amplifiers ◽  
High Efficiency ◽  
High Gain ◽  
Two Stage ◽  
Mixed Signal ◽  
Power Added Efficiency ◽  
Multi Stage ◽  
Class B

This paper presents high-efficiency high-gain 2.4 GHz power amplifiers (PAs) for wireless communications. Two class-B PAs are designed and verified in 0.13 µm CMOS mixed-signal/RF process provided by TSMC. The PAs employs cascode topologies with wideband multi-stage matchings. The single-stage cascode PA is designed for a high power added efficiency (PAE) of 35.4% while the gain is 20.4 dB over the -3 dB bandwidth between 2.4 GHz and 2.48 GHz. The two-stage cascode PA is targeted for a high gain of 37.7 dB while it exhibits a peak PAE of 24.1%. Supplied by 1.2 V supply voltages, the PAs consume DC powers of 4.5 mW and 9 mW, respectively.

A 4.2-to-5.4 GHz stacked GaAs HBT power amplifier for C-band applications

Circuit World ◽  
2020 ◽  
Vol 46 (4) ◽  
pp. 243-248
Author(s):  
Min Liu ◽  
Panpan Xu ◽  
Jincan Zhang ◽  
Bo Liu ◽  
Liwen Zhang
Keyword(s):  
Output Power ◽  
Power Amplifier ◽  
High Power ◽  
High Efficiency ◽  
Common Source ◽  
Power Performance ◽  
Matching Network ◽  
Content Type ◽  
Power Added Efficiency ◽  
Saturated Output Power

Purpose Power amplifiers (PAs) play an important role in wireless communications because they dominate system performance. High-linearity broadband PAs are of great value for potential use in multi-band system implementation. The purpose of this paper is to present a cascode power amplifier architecture to achieve high power and high efficiency requirements for 4.2∼5.4 GHz applications. Design/methodology/approach A common emitter (CE) configuration with a stacked common base configuration of heterojunction bipolar transistor (HBT) is used to achieve high power. T-type matching network is used as input matching network. To increase the bandwidth, the output matching networks are implemented using the two L-networks. Findings By using the proposed method, the stacked PA demonstrates a maximum saturated output power of 26.2 dBm, a compact chip size of 1.17 × 0.59 mm2 and a maximum power-added efficiency of 46.3 per cent. The PA shows a wideband small signal gain with less than 3 dB variation over working frequency. The saturated output power of the proposed PA is higher than 25 dBm between 4.2 and 5.4 GHz. Originality/value The technology adopted for the design of the 4.2-to-5.4 GHz stacked PA is the 2-µm gallium arsenide HBT process. Based on the proposed method, a better power performance of 3 dB improvement can be achieved as compared with the conventional CE or common-source amplifier because of high output stacking impedance.

scholarly journals X-Band High-Efficiency Continuous Class B Power Amplifier GaN MMIC Assisted by Input Second-Harmonic Tuning

Electronics ◽  
2019 ◽  
Vol 8 (11) ◽  
pp. 1312 ◽  
Author(s):  
Chen Jin ◽  
Yuan Gao ◽  
Wei Chen ◽  
Jianhua Huang ◽  
Zhiyu Wang ◽  
...  
Keyword(s):  
Power Amplifier ◽  
Integrated Circuit ◽  
High Efficiency ◽  
Second Harmonic ◽  
Power Added Efficiency ◽  
Optimum Load ◽  
Measurement Results ◽  
Class B ◽  
Point To Point ◽  
Output Capacitance

This paper presents a high-efficiency continuous class B power amplifier MMIC (Monolithic Microwave Integrated Circuit) from 8 GHz to 10.5 GHz, fabricated with 0.25 μm GaN-on-SiC technology. The Pedro load-line method was performed to calculate the optimum load of the GaN field-effect transistor (FET) for efficiency enhancement. Optimized by an output second-harmonic tuned network, fundamental to second-harmonic impedance, mapping was established point-to-point within a broad frequency band, which approached the classic continuous class B mode with an expanded high-efficiency bandwidth. Moreover, the contribution to the output capacitance of the FET was introduced into the output second-harmonic tuned network, which simplified the structure of the output matching network. Assisted by the second-harmonic source-pull technique, the input second-harmonic tuned network was optimized to improve the efficiency of the power amplifier over the operation band. The measurement results showed 51–59% PAE (Power Added Efficiency) and 19.8–21.2 dB power gain with a saturated power of 40.8–42.2 dBm from 8 GHz to 10.5 GHz. The size of the chip was 3.2 × 2.4 mm2.

A high-gain and high-efficiency X-band triaxial klystron amplifier with two-stage cascaded bunching cavities

2017 ◽  
Vol 24 (12) ◽  
pp. 123118 ◽  
Author(s):  
Wei Zhang ◽  
Jinchuan Ju ◽  
Jun Zhang ◽  
Huihuang Zhong
Keyword(s):  
High Efficiency ◽  
High Gain ◽  
Two Stage ◽  
X Band

Wideband, high-efficiency, high-power GaN amplifiers, using MIC and quasi-MMIC technologies, in the 1–4 GHz range

2014 ◽  
Vol 7 (1) ◽  
pp. 1-12 ◽  
Author(s):  
Chamssedine Berrached ◽  
Diane Bouw ◽  
Marc Camiade ◽  
Kassem El-Akhdar ◽  
Denis Barataud ◽  
...  
Keyword(s):  
Output Power ◽  
High Power ◽  
High Efficiency ◽  
Continuous Wave ◽  
Power Gain ◽  
Frequency Range ◽  
Final Size ◽  
Trade Off ◽  
Power Added Efficiency ◽  
Circuit Technology

In this paper, the designs and experimental performances of wideband (higher than one octave) high-efficiency, high-power amplifiers (HPA) working in the 1–4 GHz range, using the same GaN process, are presented. They are based on the Bode–Fano integrals, which can be applied to a trade-off calculation between bandwidth and efficiency. Firstly, an microwave intregrated circuits (MIC) wideband HPA, externally matched, is presented. It generates a continuous wave (CW) output power (Pout) greater than 40 W, a power gain (GP) higher than 9.2 dB and a corresponding power added efficiency (PAE) (drain efficiency (DE)) ranged between 36 and 44% (40 and 48%) over the 1–3 GHz bandwidth. Two other amplifiers have been designed upon the same theoretical methodology, with a passive GaAs MMIC circuit technology, enabling to reduce the final size down to 420 mm2. The first internally matched Quasi monolithic microwave intergrated circuits (Quasi-MMIC) single-ended HPA generates a pulsed Pout greater than 25 W, GP higher than 9.8 dB, and a corresponding PAE (DE) ranged between 37 and 52.5% (40 and 55%) over the 2–4 GHz bandwidth. The second internally matched Quasi-MMIC HPA, based on balanced architecture, generates a pulsed Pout higher than 45 W, GP higher than 9.5 dB and PAE (DE) ranged between 33 and 44% (38 and 50%) over the 2–4 GHz bandwidth. These results are among the best ones published in terms of PAE and Pout in instantaneous octave bandwidth in the 1–4 GHz frequency range.

A 10-W S-band class-B GaN amplifier with a dynamic gate bias circuit for linearity enhancement

2013 ◽  
Vol 6 (1) ◽  
pp. 3-11 ◽  
Author(s):  
Pierre Medrel ◽  
Audrey Martin ◽  
Tibault Reveyrand ◽  
Guillaume Neveux ◽  
Denis Barataud ◽  
...  
Keyword(s):  
Output Power ◽  
Trajectory Optimization ◽  
High Efficiency ◽  
Average Power ◽  
Gate Bias ◽  
Error Vector Magnitude ◽  
Power Added Efficiency ◽  
Class B ◽  
Band Class ◽  
A Minor

In the present paper, we present a dynamic gate biasing technique applied to a 10 W, S-band GaN amplifier. The proposed methodology addresses class-B operation of power amplifiers that offers the potential for high efficiency but requires a careful attention to maintain good linearity performances at large output power back-off. This work proposes a solution to improve the linearity of class-B amplifiers driven by radio frequency-modulated signals having large peak to average power ratios. An important aspect of this work concerns the characterization of the dynamic behavior of GaN devices for gate bias trajectory optimization. For that purpose, the experimental study reported here is based on the use of a time-domain envelope setup. A specific gate bias circuit has been designed and connected to a 10 W – 2.5 GHz GaN amplifier demo board from CREE. Compared to conventional class-B operation with a fixed gate bias, a 10-dB improvement in terms of third-order intermodulation is reached. When applied to the amplification of 16-QAM signals the proposed technique demonstrates significant ACPR reduction of order of 6 dB along with error vector magnitude (EVM) improvements of five points over 8 dB output power back-off with a minor impact on power-added efficiency performances.

Sign in / Sign up

Export Citation Format

Share Document