scholarly journals CONTROLLABLE V-SHAPE MULTISCROLL BUTTERFLY ATTRACTOR: SYSTEM AND CIRCUIT IMPLEMENTATION

2012 ◽  
Vol 22 (06) ◽  
pp. 1250143 ◽  
Author(s):  
M. AFFAN ZIDAN ◽  
A. G. RADWAN ◽  
K. N. SALAMA
Keyword(s):  
High Throughput ◽  
Field Programmable Gate Array ◽  
Small Area ◽  
Nonlinear Function ◽  
Variable Number ◽  
Experimental Results ◽  
Circuit Implementation ◽  
Digital Implementation ◽  
State Variable ◽  
Field Programmable

In this paper, a new controllable V-shape multiscroll attractor is presented, where a variety of symmetrical and unsymmetrical attractors with a variable number of scrolls can be controlled using new staircase nonlinear function and the parameters of the system. This attractor can be used to generate random signals with a variety of symbol distribution. Digital implementation of the proposed generator is also presented using a Xilinx Virtex® 4 Field Programmable Gate Array and experimental results are provided. The digital realization easily fits into a small area (<1.5% of the total area) and expresses a high throughput (4.3 Gbit/sec per state variable).

scholarly journals A digital implementation of 2D Hindmarsh–Rose neuron

2018 ◽  
Author(s):  
Nabeeh Kandalaft ◽  
Arash Ahmadi ◽  
Moslem Heidarpur
Keyword(s):  
Neural Networks ◽  
Field Programmable Gate Array ◽  
Digital Circuit ◽  
Two Dimensional ◽  
Circuit Implementation ◽  
Digital Implementation ◽  
Signal Error ◽  
Field Programmable ◽  
Implementation Costs ◽  
Hardware Costs

Different architectures and techniques havedeveloped in the neuromorphic field to mimic andinvestigate the activity of biological neural networks.This paper presents a set of piece-wise linear approximationsof a two-dimensional Hindmarsh–Rose neuronmodel for digital circuit implementation to achievehigher speeds and lower hardware costs in large-scaleimplementation of the biological neural networks. Theperformance of the model was evaluated with a timedomain signal error. Synthesis and hardware implementationon a field-programmable gate array, as aproof of concept, indicates that the proposed modelreproduces several neuronal behaviors similar to theoriginal model with higher performance and considerablylower implementation costs.

High Speed FPGA Based 128-bit Advance Encryption Standard (AES)

2021 ◽  
Vol 11 ◽  
Author(s):  
Ibrahem M. T. Hamidi ◽  
Farah S. H. Al-aassi
Keyword(s):  
High Throughput ◽  
Field Programmable Gate Array ◽  
High Speed ◽  
Design Tool ◽  
Advanced Encryption Standard ◽  
Clock Frequency ◽  
Advance Encryption Standard ◽  
Field Programmable ◽  
Internal Component ◽  
Gate Array

Aim: Achieve high throughput 128 bits FPGA based Advanced Encryption Standard. Background: Field Programmable Gate Array (FPGA) provides an efficient platform for design AES cryptography system. It provides the capability to control over each bit using HDL programming language such as VHDL and Verilog which results an output speed in Gbps rang. Objective: Use Field Programmable Gate Array (FPGA) to design high throughput 128 bits FPGA based Advanced Encryption Standard. Method: Pipelining technique has used to achieve maximum possible speed. The level of pipelining includes round pipelining and internal component pipelining where number of registers inserted in particular places to increase the output speed. The proposed design uses combinatorial logic to implement the byte substitution. The s-box implemented using composed field arithmetic with 7 stages of pipelining to reduce the combinatorial logic level. The presented model has implemented using VHDL in Xilinix ISETM 14.4 design tool. Result: The achieved results were 18.55 Gbps at a clock frequency of 144.96 MHz and area of 1568 Slices in Spartan3 xc3s1000 hardware. Conclusion: The results show that the proposed design reaches a high throughput with acceptable area usage compare with other designs in the literature.

The Design and Implementation of Parallel Distributed Algorithm FIR Filter Based on FPGA

2012 ◽  
Vol 571 ◽  
pp. 534-537
Author(s):  
Bao Feng Zhang ◽  
De Hu Man ◽  
Jun Chao Zhu
Keyword(s):  
Signal Processing ◽  
Real Time ◽  
Field Programmable Gate Array ◽  
Distributed Algorithm ◽  
Design Method ◽  
Fir Filter ◽  
Experimental Results ◽  
Linear Phase ◽  
Design And Implementation ◽  
Field Programmable

The article proposed a new method for implementing linear phase FIR filter based on FPGA. For the key to implementing the FIR filter on FPGA—multiply-add operation, a parallel distributed algorithm was presented, which is based on LUT. The designed file was described with VHDL and realized on Altera’s field programmable gate array (FPGA), giving the design method. The experimental results indicated that the system can run stably at 120MHz or more, which can meet the requirements of signal processing for real-time.

Memristor Oscillators and its FPGA Implementation

2011 ◽  
Vol 383-390 ◽  
pp. 6992-6997 ◽  
Author(s):  
Ai Xue Qi ◽  
Cheng Liang Zhang ◽  
Guang Yi Wang
Keyword(s):  
Numerical Simulation ◽  
Chaotic System ◽  
Field Programmable Gate Array ◽  
Chaotic Attractor ◽  
Hardware Implementation ◽  
Fpga Implementation ◽  
Experimental Results ◽  
Linear Resistance ◽  
Non Linear ◽  
Field Programmable

This paper presents a method that utilizes a memristor to replace the non-linear resistance of typical Chua’s circuit for constructing a chaotic system. The improved circuit is numerically simulated in the MATLAB condition, and its hardware implementation is designed using field programmable gate array (FPGA). Comparing the experimental results with the numerical simulation, the two are the very same, and be able to generate chaotic attractor.

scholarly journals A High Throughput Hardware Architecture for Parallel Recursive Systematic Convolutional Encoders

Information ◽  
2019 ◽  
Vol 10 (4) ◽  
pp. 151
Author(s):  
Gabriele Meoni ◽  
Gianluca Giuffrida ◽  
Luca Fanucci
Keyword(s):  
High Throughput ◽  
Network Topology ◽  
Bit Error Rate ◽  
Error Rate ◽  
Field Programmable Gate Array ◽  
Input Data ◽  
Telecommunication Systems ◽  
Hardware Implementations ◽  
Field Programmable ◽  
Convolutional Encoders

During the last years, recursive systematic convolutional (RSC) encoders have found application in modern telecommunication systems to reduce the bit error rate (BER). In view of the necessity of increasing the throughput of such applications, several approaches using hardware implementations of RSC encoders were explored. In this paper, we propose a hardware intellectual property (IP) for high throughput RSC encoders. The IP core exploits a methodology based on the ABCD matrices model which permits to increase the number of inputs bits processed in parallel. Through an analysis of the proposed network topology and by exploiting data relative to the implementation on Zynq 7000 xc7z010clg400-1 field programmable gate array (FPGA), an estimation of the dependency of the input data rate and of the source occupation on the parallelism degree is performed. Such analysis, together with the BER curves, provides a description of the principal merit parameters of a RSC encoder.

scholarly journals Enabling Packet Classification with Low Update Latency for SDN Switch on FPGA

2020 ◽  
Vol 12 (8) ◽  
pp. 3068 ◽  
Author(s):  
Chenglong Li ◽  
Tao Li ◽  
Junnan Li ◽  
Zilin Shi ◽  
Baosheng Wang
Keyword(s):  
Real Time ◽  
Field Programmable Gate Array ◽  
High Performance ◽  
Recursive Algorithm ◽  
Packet Classification ◽  
Experimental Results ◽  
The Core ◽  
Core Function ◽  
Field Programmable ◽  
Bit Vector

Field Programmable Gate Array (FPGA) is widely used in real-time network processing such as Software-Defined Networking (SDN) switch due to high performance and programmability. Bit-Vector (BV)-based approaches can implement high-performance multi-field packet classification, on FPGA, which is the core function of the SDN switch. However, the SDN switch requires not only high performance but also low update latency to avoid controller failure. Unfortunately, the update latency of BV-based approaches is inversely proportional to the number of rules, which means can hardly support the SDN switch effectively. It is reasonable to split the ruleset into sub-rulesets that can be performed in parallel, thereby reducing update latency. We thus present SplitBV for the efficient update by using several distinguishable exact-bits to split the ruleset. SplitBV consists of a constrained recursive algorithm for selecting the bit positions that can minimize the latency and a hybrid lookup pipeline. It can achieve a significant reduction in update latency with negligible memory growth and comparable high performance. We implement SplitBV and evaluate its performance by simulation and FPGA prototype. Experimental results show that our approach can reduce 73% and 36% update latency on average for synthetic 5-tuple rules and OpenFlow rules respectively.

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