Dynamic Laser Delay Variation Mapping (DVM) Implementations and Applications

2005 ◽  
Author(s):  
Kevin Sanchez ◽  
Romain Desplats ◽  
Philippe Perdu ◽  
Felix Beaudoin ◽  
Sylvain Dudit ◽  
...  
Keyword(s):  
Integrated Circuit ◽  
Functional Tests ◽  
Laser Stimulation ◽  
Application Field ◽  
Defect Localization ◽  
Delay Variation

Abstract In this paper we report on the application field of Dynamic Laser Stimulation (DLS) techniques to Integrated Circuit (IC) analysis. The effects of thermal and photoelectric laser stimulation on ICs are presented. Implementations, practical considerations and applications are presented for techniques based on functional tests like Soft Defect Localization (SDL) and Laser Assisted Device Alteration (LADA). A new methodology, Delay Variation Mapping (DVM), will also be presented and discussed.

Case Study: Combined Dynamic Laser Stimulation and Static Emission Microscopy Techniques Applied to Scan Test Failure on Mixed Mode Device

2012 ◽  
Author(s):  
Magdalena Sienkiewicz ◽  
Philippe Rousseille
Keyword(s):  
Mixed Mode ◽  
Laser Stimulation ◽  
Scan Test ◽  
Silicon Bulk ◽  
Defect Localization ◽  
Emission Microscopy ◽  
Microscopy Techniques ◽  
Test Failure

Abstract This paper presents a case study on scan test reject in a mixed mode IC. It focuses on the smart use of combined mature FA techniques, such as Soft Defect Localization (SDL) and emission microscopy (EMMI), to localize a random scan test anomaly at the silicon bulk level.

scholarly journals Preliminary Study on the Model of Thermal Laser Stimulation for Defect Localization in Integrated Circuits

2020 ◽  
Vol 10 (23) ◽  
pp. 8576
Author(s):  
Han Yang ◽  
Rui Chen ◽  
Jianwei Han ◽  
Yanan Liang ◽  
Yingqi Ma ◽  
...  
Keyword(s):  
Integrated Circuits ◽  
Induced Resistance ◽  
Seebeck Effect ◽  
Comprehensive Model ◽  
Induced Voltage ◽  
Efficient Technology ◽  
Resistance Change ◽  
Scanning Velocity ◽  
Laser Stimulation ◽  
Defect Localization

Thermal Laser Stimulation (TLS) is an efficient technology for integrated circuit defect localization in Failure Analysis (FA) laboratories. It contains Optical Beam-Induced Resistance Change (OBIRCH), Thermally-Induced Voltage Alteration (TIVA), and Seebeck Effect Imaging (SEI). These techniques respectively use the principle of laser-induced resistance change and the Seebeck effect. In this paper, a comprehensive model of TLS technology is proposed. Firstly, the model presents an analytical expression of the temperature variation in Integrated Circuits (IC) after laser irradiation, which quantificationally shows the positive correlation with laser power and the negative correlation with scanning velocity. Secondly, the model describes the opposite influence of laser-induced resistance change and the Seebeck effect in the device. Finally, the relationship between the current variation measured in the experiment and other parameters, especially the voltage bias, is well explained by the model. The comprehensive model provides theoretical guidance for the efficient and accurate defect localization of TLS technology.

Precise Defect Localization of Scan Logic Failures by Thermal Laser Stimulation (TLS)

2004 ◽  
Author(s):  
Zhongling Qian ◽  
Christof Brillert ◽  
Christian Burmer ◽  
Peter Egger
Keyword(s):  
Fault Diagnosis ◽  
Analysis Time ◽  
Scan Design ◽  
Additional Method ◽  
Localization Accuracy ◽  
Laser Stimulation ◽  
Defect Localization

Abstract Scan design in modern advanced ICs has enabled the software-based fault diagnosis. It is a powerful tool for localization of defects. However, according to fault diagnosis, there are sometimes many defect candidates and each defect candidate can have many equivalent nets. These nets may be distributed widely, even over the whole chip. Therefore, an additional method of precise defect localization is needed as a complement. In this paper, the TLS method (Thermal Laser Stimulation) is utilized with a simplified setup for this purpose. It shows that the correlation between TLS inspection and scan diagnosis significantly saves analysis time due to the improvement of localization accuracy of the corresponding physical defect.

Leakage current study and relevant defect localization in integrated circuit failure analysis

2015 ◽  
Vol 55 (3-4) ◽  
pp. 463-469 ◽  
Author(s):  
Chunlei Wu ◽  
Suying Yao ◽  
Bergès Corinne
Keyword(s):  
Failure Analysis ◽  
Leakage Current ◽  
Integrated Circuit ◽  
Defect Localization

Laser Scanning Localization Technique for Fast Analysis of High Speed DRAM Devices

2008 ◽  
Author(s):  
Martin Versen ◽  
Achim Schramm ◽  
Jan Schnepp ◽  
Sascha Hoch ◽  
Tapan Vikas ◽  
...  
Keyword(s):  
Integrated Circuit ◽  
High Speed ◽  
Laser Scanning ◽  
Random Access ◽  
Laser Scanning Microscopy ◽  
New Method ◽  
Temperature Influence ◽  
Fast Analysis ◽  
Knowledge Based ◽  
Defect Localization

Abstract Soft defect localization (SDL) is a method of laser scanning microscopy that utilizes the changing pass/fail behavior of an integrated circuit under test and temperature influence. Historically the pass and fail states are evaluated by a tester that leads to long and impracticable measurement times for dynamic random access memories (DRAM). The new method using a high speed comparison device allows SDL image acquisition times of a few minutes and a localization of functional DRAM fails that are caused by defects in the DRAM periphery that has not been possible before. This new method speeds up significantly the turn-around time in the failure analysis (FA) process compared to knowledge based FA.

Delay variation mapping induced by dynamic laser stimulation

2005 ◽  
Author(s):  
K. Sanchez ◽  
R. Deplats ◽  
F. Beaudoin ◽  
P. Perdu ◽  
D. Lewis ◽  
...  
Keyword(s):  
Laser Stimulation ◽  
Delay Variation
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