Fault Isolation on High Resistance Failure of 45nm ET Via Chains Using Combined Technique of SEM PVC and Nanoprobing

2010 ◽  
Author(s):  
P.K. Tan ◽  
Z.H. Mai ◽  
Y.W. Goh ◽  
L. Zhu ◽  
S.L. Toh ◽  
...  
Keyword(s):  
Electron Microscope ◽  
High Resistance ◽  
Fault Isolation ◽  
Divide And Conquer ◽  
Electrical Performance ◽  
Process Line ◽  
Scaling Down ◽  
Voltage Contrast ◽  
Combined Technique ◽  
Scanning Electron

Abstract Electrical Test (ET) structures are used to monitor the health and yield of a process line. With the scaling down of semiconductor devices to nanometer ranges, the number of metal lines and vias increase. In order to simulate the electrical performance of devices and to increase the sensitivity for line health check, ET structures are designed to be more complicated with a larger area. Hence, fault isolation and failure analysis become more challenging. In this paper, the combined technique of Scanning Electron Microscope (SEM) Passive Voltage Contrast (PVC), Nanoprobing technique, and Divide and Conquer Method (DCM) are proposed to locate open failure and high resistance failure in an ET via chain.

Fault Identification by Use of a Simulated Passive Voltage Contrast Reference CAD Display

2006 ◽  
Author(s):  
R. Fredrickson
Keyword(s):  
Electron Microscope ◽  
Scanning Electron Microscope ◽  
Semiconductor Device ◽  
Fault Isolation ◽  
Fault Identification ◽  
Circuit Element ◽  
Design Rules ◽  
Voltage Contrast ◽  
Scanning Electron ◽  
Open Connection

Abstract Passive voltage contrast (PVC) is a phenomenon seen while inspecting a semiconductor device where imaged circuit features have a different value of contrast depending on whether that feature has an electrical path to ground, another circuit element, or has an open connection. A common method of fault isolation during failure analysis is to use these contrast values to determine if a feature is incorrectly connected indicating a defect is present. This paper discusses a fault identification method by creating a simulated PVC reference that can be displayed next to the scanning electron microscope PVC image for a comparison of the expected PVC. The procedure of how to create the PVC reference is discussed using functions found in tools typically used to run a Design Rules Check in commonly available software. Three examples are given of how this methodology could be used to provide further analysis capabilities during fault isolation.

Electrical Characterization of Different Failure Modes in Sub-100 nm Devices Using Nanoprobing Technique

2009 ◽  
Author(s):  
E. Hendarto ◽  
S.L. Toh ◽  
J. Sudijono ◽  
P.K. Tan ◽  
H. Tan ◽  
...  
Keyword(s):  
Electron Microscope ◽  
Focused Ion Beam ◽  
Failure Modes ◽  
Ion Beam ◽  
Electrical Characterization ◽  
Nickel Silicide ◽  
Fault Isolation ◽  
Technology Nodes ◽  
Scanning Electron

Abstract The scanning electron microscope (SEM) based nanoprobing technique has established itself as an indispensable failure analysis (FA) technique as technology nodes continue to shrink according to Moore's Law. Although it has its share of disadvantages, SEM-based nanoprobing is often preferred because of its advantages over other FA techniques such as focused ion beam in fault isolation. This paper presents the effectiveness of the nanoprobing technique in isolating nanoscale defects in three different cases in sub-100 nm devices: soft-fail defect caused by asymmetrical nickel silicide (NiSi) formation, hard-fail defect caused by abnormal NiSi formation leading to contact-poly short, and isolation of resistive contact in a large electrical test structure. Results suggest that the SEM based nanoprobing technique is particularly useful in identifying causes of soft-fails and plays a very important role in investigating the cause of hard-fails and improving device yield.

Failure Analysis of Killer Defects and Yield Enhancement of Flat ROM Devices in Wafer Fabrication

2000 ◽  
Author(s):  
Y. N. Hua ◽  
Z. R. Guo ◽  
L. H. An ◽  
Shailesh Redkar
Keyword(s):  
Electron Microscope ◽  
Failure Analysis ◽  
Fault Isolation ◽  
Yield Enhancement ◽  
Wafer Fabrication ◽  
X Ray ◽  
Particle Contamination ◽  
Emission Microscopy ◽  
Microscopy Techniques ◽  
Scanning Electron

Abstract In this paper, some low yield cases in Flat ROM device (0.45 and 0.6 µm) were investigated. To find killer defects and particle contamination, KLA, bitmap and emission microscopy techniques were used in fault isolation. Reactive ion etching (RIE) and chemical delayering, 155 Wright Etch, BN+ Etch and scanning electron microscope (SEM) were used for identification and inspection of defects. In addition, energy-dispersive X-ray microanalysis (EDX) was used to determine the composition of the particle or contamination. During failure analysis, seven kinds of killer defects and three killer particles were found in Flat ROM devices. The possible root causes, mechanisms and elimination solutions of these killer defects/particles were also discussed.

Solving the Voltage Contrast on Floating Substrate with Standard FA Toolset

2016 ◽  
Author(s):  
Julien Goxe ◽  
Béatrice Vanhuffel ◽  
Marie Castignolles ◽  
Thomas Zirilli
Keyword(s):  
Electron Microscope ◽  
Scanning Electron Microscope ◽  
Sample Preparation ◽  
Failure Analysis ◽  
Focused Ion Beam ◽  
Ion Beam ◽  
Silicon On Insulator ◽  
Mixed Signal ◽  
Voltage Contrast ◽  
Scanning Electron

Abstract Passive Voltage Contrast (PVC) in a Scanning Electron Microscope (SEM) or a Focused Ion Beam (FIB) is a key Failure Analysis (FA) technique to highlight a leaky gate. The introduction of Silicon On Insulator (SOI) substrate in our recent automotive analog mixed-signal technology highlighted a new challenge: the Bottom Oxide (BOX) layer, by isolating the Silicon Active Area from the bulk made PVC technique less effective in finding leaky MOSFET gates. A solution involving sample preparation performed with standard FA toolset is proposed to enhance PVC on SOI substrate.

Circuit Tracing on Integrated Circuit Using FIB Passive Voltage Contrast Effect

2015 ◽  
Author(s):  
Alexander Sorkin ◽  
Chris Pawlowicz ◽  
Alex Krechmer ◽  
Michael W. Phaneuf
Keyword(s):  
Electron Microscope ◽  
Integrated Circuits ◽  
Integrated Circuit ◽  
Metal Layer ◽  
Database System ◽  
Conventional Procedure ◽  
Sem Imaging ◽  
Voltage Contrast ◽  
Scanning Electron ◽  
Graphic Database

Abstract Competitive circuit analysis of Integrated Circuits (ICs) is one of the most challenging types of analysis. It involves multiple complex IC die de-processing/de-layering steps while keeping precise planarity from metal layer to metal layer. Each step is followed by Scanning Electron Microscope (SEM) imaging together with mosaicking that subsequently passes through an image recognition and Graphic Database System (GDS) conversion process. This conventional procedure is quite time and resource consuming. The current paper discusses and demonstrates a new inventive methodology of circuit tracing on an IC using known FIB Passive Voltage Contrast (PVC) effects [1]. This technique provides significant savings in time and resources.

Failure Analysis of FinFET Circuitry at GHz Speeds Using Voltage-Contrast and Stroboscopic Techniques on a Scanning Electron Microscope

2019 ◽  
Author(s):  
James Vickers ◽  
Seema Somani ◽  
Blake Freeman ◽  
Pete Carleson ◽  
Lubomír Tùma ◽  
...  
Keyword(s):  
Electron Microscope ◽  
Scanning Electron Microscope ◽  
Integrated Circuits ◽  
Electrical Activity ◽  
Failure Analysis ◽  
Integrated Circuit ◽  
Contrast Mechanism ◽  
Voltage Contrast ◽  
Working Device ◽  
Scanning Electron

Abstract We report on using the voltage-contrast mechanism of a scanning electron microscope to probe electrical waveforms on FinFET transistors that are located within active integrated circuits. The FinFET devices are accessed from the backside of the integrated circuit, enabling electrical activity on any transistor within a working device to be probed. We demonstrate gigahertz-bandwidth probing at 10-nm resolution using a stroboscopic pulsed electron source.

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