Failure Analysis of FinFET Circuitry at GHz Speeds Using Voltage-Contrast and Stroboscopic Techniques on a Scanning Electron Microscope

2019 ◽  
Author(s):  
James Vickers ◽  
Seema Somani ◽  
Blake Freeman ◽  
Pete Carleson ◽  
Lubomír Tùma ◽  
...  
Keyword(s):  
Electron Microscope ◽  
Scanning Electron Microscope ◽  
Integrated Circuits ◽  
Electrical Activity ◽  
Failure Analysis ◽  
Integrated Circuit ◽  
Contrast Mechanism ◽  
Voltage Contrast ◽  
Working Device ◽  
Scanning Electron

Abstract We report on using the voltage-contrast mechanism of a scanning electron microscope to probe electrical waveforms on FinFET transistors that are located within active integrated circuits. The FinFET devices are accessed from the backside of the integrated circuit, enabling electrical activity on any transistor within a working device to be probed. We demonstrate gigahertz-bandwidth probing at 10-nm resolution using a stroboscopic pulsed electron source.

Failure Analysis With the Scanning Electron Microscope

1972 ◽  
Vol 30 ◽  
pp. 482-483
Author(s):  
John R. Devaney
Keyword(s):  
Electron Microscope ◽  
Scanning Electron Microscope ◽  
Integrated Circuits ◽  
Failure Analysis ◽  
High Reliability ◽  
Military Applications ◽  
Small Structure ◽  
Useful Life ◽  
Insight Into ◽  
Scanning Electron

Occasionally in history, an event may occur which has a profound influence on a technology. Such an event occurred when the scanning electron microscope became commercially available to industry in the mid 60's. Semiconductors were being increasingly used in high-reliability space and military applications both because of their small volume but, also, because of their inherent reliability. However, they did fail, both early in life and sometimes in middle or old age. Why they failed and how to prevent failure or prolong “useful life” was a worry which resulted in a blossoming of sophisticated failure analysis laboratories across the country. By 1966, the ability to build small structure integrated circuits was forging well ahead of techniques available to dissect and analyze these same failures. The arrival of the scanning electron microscope gave these analysts a new insight into failure mechanisms.

Solving the Voltage Contrast on Floating Substrate with Standard FA Toolset

2016 ◽  
Author(s):  
Julien Goxe ◽  
Béatrice Vanhuffel ◽  
Marie Castignolles ◽  
Thomas Zirilli
Keyword(s):  
Electron Microscope ◽  
Scanning Electron Microscope ◽  
Sample Preparation ◽  
Failure Analysis ◽  
Focused Ion Beam ◽  
Ion Beam ◽  
Silicon On Insulator ◽  
Mixed Signal ◽  
Voltage Contrast ◽  
Scanning Electron

Abstract Passive Voltage Contrast (PVC) in a Scanning Electron Microscope (SEM) or a Focused Ion Beam (FIB) is a key Failure Analysis (FA) technique to highlight a leaky gate. The introduction of Silicon On Insulator (SOI) substrate in our recent automotive analog mixed-signal technology highlighted a new challenge: the Bottom Oxide (BOX) layer, by isolating the Silicon Active Area from the bulk made PVC technique less effective in finding leaky MOSFET gates. A solution involving sample preparation performed with standard FA toolset is proposed to enhance PVC on SOI substrate.

Circuit Tracing on Integrated Circuit Using FIB Passive Voltage Contrast Effect

2015 ◽  
Author(s):  
Alexander Sorkin ◽  
Chris Pawlowicz ◽  
Alex Krechmer ◽  
Michael W. Phaneuf
Keyword(s):  
Electron Microscope ◽  
Integrated Circuits ◽  
Integrated Circuit ◽  
Metal Layer ◽  
Database System ◽  
Conventional Procedure ◽  
Sem Imaging ◽  
Voltage Contrast ◽  
Scanning Electron ◽  
Graphic Database

Abstract Competitive circuit analysis of Integrated Circuits (ICs) is one of the most challenging types of analysis. It involves multiple complex IC die de-processing/de-layering steps while keeping precise planarity from metal layer to metal layer. Each step is followed by Scanning Electron Microscope (SEM) imaging together with mosaicking that subsequently passes through an image recognition and Graphic Database System (GDS) conversion process. This conventional procedure is quite time and resource consuming. The current paper discusses and demonstrates a new inventive methodology of circuit tracing on an IC using known FIB Passive Voltage Contrast (PVC) effects [1]. This technique provides significant savings in time and resources.

Linewidth measurement using the low voltage SEM

1986 ◽  
Vol 44 ◽  
pp. 652-653
Author(s):  
M.G. Rosenfield
Keyword(s):  
Electron Microscope ◽  
Scanning Electron Microscope ◽  
Integrated Circuits ◽  
Secondary Electron ◽  
Low Voltage ◽  
Fabrication Process ◽  
Critical Dimensions ◽  
Linewidth Measurement ◽  
Threshold Technique ◽  
Scanning Electron

Minimum feature sizes in experimental integrated circuits are approaching 0.5 μm and below. During the fabrication process it is usually necessary to be able to non-destructively measure the critical dimensions in resist and after the various process steps. This can be accomplished using the low voltage SEM. Submicron linewidth measurement is typically done by manually measuring the SEM micrographs. Since it is desirable to make as many measurements as possible in the shortest period of time, it is important that this technique be automated.Linewidth measurement using the scanning electron microscope is not well understood. The basic intent is to measure the size of a structure from the secondary electron signal generated by that structure. Thus, it is important to understand how the actual dimension of the line being measured relates to the secondary electron signal. Since different features generate different signals, the same method of relating linewidth to signal cannot be used. For example, the peak to peak method may be used to accurately measure the linewidth of an isolated resist line; but, a threshold technique may be required for an isolated space in resist.

Using the scanning electron microscope for failure analysis of high density magnetic media

1987 ◽  
Vol 45 ◽  
pp. 392-393
Author(s):  
Evelyn R. Ackerman ◽  
Gary D. Burnett
Keyword(s):  
Electron Microscope ◽  
Scanning Electron Microscope ◽  
Failure Analysis ◽  
High Density ◽  
Magnetic Media ◽  
Specific Data ◽  
Retrieval Systems ◽  
Operating Environments ◽  
The Media ◽  
Scanning Electron

Advancements in state of the art high density Head/Disk retrieval systems has increased the demand for sophisticated failure analysis methods. From 1968 to 1974 the emphasis was on the number of tracks per inch. (TPI) ranging from 100 to 400 as summarized in Table 1. This emphasis shifted with the increase in densities to include the number of bits per inch (BPI). A bit is formed by magnetizing the Fe203 particles of the media in one direction and allowing magnetic heads to recognize specific data patterns. From 1977 to 1986 the tracks per inch increased from 470 to 1400 corresponding to an increase from 6300 to 10,800 bits per inch respectively. Due to the reduction in the bit and track sizes, build and operating environments of systems have become critical factors in media reliability.Using the Ferrofluid pattern developing technique, the scanning electron microscope can be a valuable diagnostic tool in the examination of failure sites on disks.

SEM-Based Nanoprobing on 40, 32 and 28 nm CMOS Devices Challenges for Semiconductor Failure Analysis

2013 ◽  
Author(s):  
Erik Paul ◽  
Holger Herzog ◽  
Sören Jansen ◽  
Christian Hobert ◽  
Eckhard Langer
Keyword(s):  
Electron Microscope ◽  
High Resolution ◽  
Scanning Electron Microscope ◽  
Failure Analysis ◽  
Case Studies ◽  
State Of The Art ◽  
Root Cause ◽  
Highly Efficient ◽  
Technology Nodes ◽  
Scanning Electron

Abstract This paper presents an effective device-level failure analysis (FA) method which uses a high-resolution low-kV Scanning Electron Microscope (SEM) in combination with an integrated state-of-the-art nanomanipulator to locate and characterize single defects in failing CMOS devices. The presented case studies utilize several FA-techniques in combination with SEM-based nanoprobing for nanometer node technologies and demonstrate how these methods are used to investigate the root cause of IC device failures. The methodology represents a highly-efficient physical failure analysis flow for 28nm and larger technology nodes.

A Working Method for Adapting the (SEM) Scanning Electron Microscope to Produce (STEM) Scanning Transmission Electron Microscope Images

2002 ◽  
Author(s):  
Edward Coyne
Keyword(s):  
Electron Microscope ◽  
High Resolution ◽  
Scanning Electron Microscope ◽  
Integrated Circuits ◽  
Theoretical Idea ◽  
Cross Sectional ◽  
Additional Advantage ◽  
Transmission Electron ◽  
Resolution Element ◽  
Scanning Electron

Abstract This paper describes the problems encountered and solutions found to the practical objective of developing an imaging technique that would produce a more detailed analysis of IC material structures then a scanning electron microscope. To find a solution to this objective the theoretical idea of converting a standard SEM to produce a STEM image was developed. This solution would enable high magnification, material contrasting, detailed cross sectional analysis of integrated circuits with an ordinary SEM. This would provide a practical and cost effective alternative to Transmission Electron Microscopy (TEM), where the higher TEM accelerating voltages would ultimately yield a more detailed cross sectional image. An additional advantage, developed subsequent to STEM imaging was the use of EDX analysis to perform high-resolution element identification of IC cross sections. High-resolution element identification when used in conjunction with high-resolution STEM images provides an analysis technique that exceeds the capabilities of conventional SEM imaging.

Scanning Electron Microscope Induced Electrical Breakdown of Tungsten Windows in Integrated Circuit Processing

2004 ◽  
Author(s):  
David M. Shuttleworth ◽  
Mary Drummond Roby
Keyword(s):  
Electron Microscope ◽  
Scanning Electron Microscope ◽  
Contact Resistance ◽  
Integrated Circuit ◽  
Electrical Breakdown ◽  
Scanning Electron ◽  
Integrated Circuit Processing

Abstract Interaction of inline SEM inspections with tungsten window-1 integrity were investigated. Multiple SEMs were utilized and various points in the processing were inspected. It was found that in certain circumstances inline SEM inspection induced increased window-1 contact resistance in both source/drain and gate contacts, up to and including electrical opens for the source/drain contacts.

scholarly journals Automatic Integrated Circuit Die Positioning in the Scanning Electron Microscope

Scanning ◽  
2006 ◽  
Vol 24 (2) ◽  
pp. 86-91 ◽  
Author(s):  
H. W. Tan ◽  
J. C. H. Phang ◽  
J. T. L. Thong
Keyword(s):  
Electron Microscope ◽  
Scanning Electron Microscope ◽  
Integrated Circuit ◽  
Scanning Electron
Sign in / Sign up

Export Citation Format

Share Document