A new extension method of retention time for memory cell on dynamic random access memory

Integration ◽  
2014 ◽  
Vol 47 (3) ◽  
pp. 329-338 ◽  
Author(s):  
Yoshiro Riho ◽  
Kazuo Nakazato
Keyword(s):  
Retention Time ◽  
Random Access ◽  
Memory Cell ◽  
Random Access Memory ◽  
Dynamic Random Access Memory ◽  
Access Memory ◽  
Extension Method

Analysis of Grain Boundary Dependent Memory Characteristics in Poly-Si One-Transistor Dynamic Random-Access Memory

2021 ◽  
Vol 21 (8) ◽  
pp. 4216-4222
Author(s):  
Songyi Yoo ◽  
In-Man Kang ◽  
Sung-Jae Cho ◽  
Wookyung Sun ◽  
Hyungsoon Shin
Keyword(s):  
Strong Electric Field ◽  
Memory Performance ◽  
Random Access ◽  
Memory Cell ◽  
Random Access Memory ◽  
Dynamic Random Access Memory ◽  
Thin Body ◽  
Memory Cells ◽  
Access Memory ◽  
Memory Characteristics

A capacitorless one-transistor dynamic random-access memory cell with a polysilicon body (poly-Si 1T-DRAM) has a cost-effective fabrication process and allows a three-dimensional stacked architecture that increases the integration density of memory cells. Also, since this device uses grain boundaries (GBs) as a storage region, it can be operated as a memory cell even in a thin body device. GBs are important to the memory characteristics of poly-Si 1T-DRAM because the amount of trapped charge in the GBs determines the memory’s data state. In this paper, we report on a statistical analysis of the memory characteristics of poly-Si 1T-DRAM cells according to the number and location of GBs using TCAD simulation. As the number of GBs increases, the sensing margin and retention time of memory cells deteriorate due to increasing trapped electron charge. Also, “0” state current increases and memory performance degrades in cells where all GBs are adjacent to the source or drain junction side in a strong electric field. These results mean that in poly-Si 1T-DRAM design, the number and location of GBs in a channel should be considered for optimal memory performance.

A 1T Dynamic Random Access Memory Cell Based on Gated Thyristor with Surrounding Gate Structure for High Scalability

2018 ◽  
Vol 18 (9) ◽  
pp. 5919-5924
Author(s):  
Hyungjin Kim ◽  
Sihyun Kim ◽  
Hyun-Min Kim ◽  
Kitae Lee ◽  
Sangwan Kim ◽  
...  
Keyword(s):  
Random Access ◽  
Memory Cell ◽  
Random Access Memory ◽  
Dynamic Random Access Memory ◽  
Access Memory ◽  
Gate Structure ◽  
Surrounding Gate ◽  
High Scalability

Nanoscale CuO solid-electrolyte-based conductive-bridging-random-access-memory cell operating multi-level-cell and 1selector1resistor

2015 ◽  
Vol 3 (37) ◽  
pp. 9540-9550 ◽  
Author(s):  
Kyoung-Cheol Kwon ◽  
Myung-Jin Song ◽  
Ki-Hyun Kwon ◽  
Han-Vit Jeoung ◽  
Dong-Won Kim ◽  
...  
Keyword(s):  
Solid Electrolyte ◽  
Retention Time ◽  
Random Access ◽  
Memory Cell ◽  
Random Access Memory ◽  
Access Memory ◽  
Multi Level

Nanoscale non-volatile CBRAM-cells are developed by using a CuO solid-electrolyte, providing a ∼102memory margin, ∼3 × 106endurance cycles, ∼6.63-years retention time at 85 °C, ∼100 ns writing speed, and MLC operation.

A New Approach for Screening Retention Time Failure Bits in DRAM Device

2013 ◽  
Author(s):  
Bonggu Sung ◽  
Daejung Kim ◽  
Yongjik Park ◽  
Joo-Sun Choi
Keyword(s):  
Retention Time ◽  
Random Access ◽  
Random Access Memory ◽  
Cell Plate ◽  
Dynamic Random Access Memory ◽  
Access Memory ◽  
New Approach ◽  
Root Cause ◽  
Storage Node ◽  
Node Voltage

Abstract In this paper, we investigate that Gate-Induced Drain Leakage (GIDL)-weak cells can be screened effectively by modulation of cell-plate voltage (VPlate) during retention time in dynamic random access memory (DRAM) with Negative Wordline bias scheme (NWL). Boosting storage-node voltage (VSP) by increase of VPlate is the root cause of generating additional GIDL fail bits.

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