scholarly journals Simplifying the Boolean Equation Based on Simulation System using Karnaugh Mapping Tool in Digital Circuit Design

2021 ◽  
pp. 76-84
Author(s):  
Md Jahidul Islam ◽  
Md Gulzar Hussain ◽  
Babe Sultana ◽  
Mahmuda Rahman ◽  
Md Saidur Rahman ◽  
...  
Keyword(s):  
Integrated Circuits ◽  
Computational Cost ◽  
Computation Time ◽  
Digital Circuit ◽  
Fundamental Principle ◽  
Algebraic Expression ◽  
Mapping Tool ◽  
Digital Circuit Design ◽  
Boolean Equation ◽  
Karnaugh Map

In computerized integrated circuits, the fundamental principle intends to avoid the multifaceted nature of the circuitry by making it as brief as attainable and minimize the expenditure. Techniques like Quine- McCluskey (QM) and Karnaugh Map (K-Map) are often used approaches of simplifying Boolean functions. This study presents a recreation framework of simplification of the Boolean capacities by the utilize of the K- Map definition for beginner-level learners. It uses the algebraic expression of the Boolean function to decrease the number of terms, generates a circuit, and does not use any redundant sets. In this way, it gets to be competent to deal with lots of parameters and minimize the computational cost. The result of the assessment is performed in this paper by contrasting it with the C- Minimizer algorithm. In computation time terms, the result appears that our comprehensive K mapping tool outflanks in current procedures, and the relative error accomplishes a lower rate of percentage (2%), which fulfills the satisfactory level. GUB JOURNAL OF SCIENCE AND ENGINEERING, Vol 7, Dec 2020 P 76-84

scholarly journals Computational Performance Optimisation for Statistical Analysis of the Effect of Nano-CMOS Variability on Integrated Circuits

VLSI Design ◽  
2013 ◽  
Vol 2013 ◽  
pp. 1-22
Author(s):  
Zheng Xie ◽  
Doug Edwards
Keyword(s):  
Integrated Circuits ◽  
Computational Cost ◽  
Computation Time ◽  
Cmos Technology ◽  
Intrinsic Variability ◽  
Circuit Element ◽  
Computational Performance ◽  
Vlsi Technology ◽  
Complex Circuits

The intrinsic variability of nanoscale VLSI technology must be taken into account when analyzing circuit designs to predict likely yield. Monte-Carlo- (MC-) and quasi-MC- (QMC-) based statistical techniques do this by analysing many randomised or quasirandomised copies of circuits. The randomisation must model forms of variability that occur in nano-CMOS technology, including “atomistic” effects without intradie correlation and effects with intradie correlation between neighbouring devices. A major problem is the computational cost of carrying out sufficient analyses to produce statistically reliable results. The use of principal components analysis, behavioural modeling, and an implementation of “Statistical Blockade” (SB) is shown to be capable of achieving significant reduction in the computational costs. A computation time reduction of 98.7% was achieved for a commonly used asynchronous circuit element. Replacing MC by QMC analysis can achieve further computation reduction, and this is illustrated for more complex circuits, with the results being compared with those of transistor-level simulations. The “yield prediction” analysis of SRAM arrays is taken as a case study, where the arrays contain up to 1536 transistors modelled using parameters appropriate to 35 nm technology. It is reported that savings of up to 99.85% in computation time were obtained.

Linear Integrated Circuit Design in the Curriculum

1982 ◽  
Vol 19 (3) ◽  
pp. 265-270
Author(s):  
H. E. Hanrahan ◽  
S. J. West
Keyword(s):  
Integrated Circuits ◽  
Circuit Design ◽  
Integrated Circuit ◽  
Common Ground ◽  
Digital Circuit ◽  
Digital Design ◽  
Integrated Circuit Design ◽  
Digital Circuit Design ◽  
Basic Concepts ◽  
Tools And Techniques

Recent advances in VLSI digital circuit design methods and the silicon foundry concept has put the design of such circuits within reach of students. This paper discusses the design of linear integrated circuits by students. The basic concepts, tools and techniques are reviewed. The areas of common ground and differences between analogue and digital design techniques are highlighted.

scholarly journals Handling Generalized Type-2 Problems of Digital Circuit Design via the Variable-Entered Karnaugh Map

2018 ◽  
Vol 3 (4) ◽  
pp. 392-403 ◽  
Author(s):  
Rushdi Rushdi
Keyword(s):  
Circuit Design ◽  
Fundamental Problem ◽  
Digital Circuit ◽  
Novel Treatment ◽  
Digital Circuit Design ◽  
Input Domain ◽  
Karnaugh Map ◽  
Generalized Type

This paper offers a novel treatment of the generalized Type-2 problem, a prominent fundamental problem of digital circuit design. We adapt the input-domain constraining technique via utilization of Variable-Entered Karnaugh Maps (VEKMs) together with careful employment of modern don’t-care notation. Our analysis covers the cases when an honest translator is possible or a sneaky translator is warranted, and is effective whether side inputs are absent or present, and for scalar or vectorial outputs.

scholarly journals Digital Circuit Design Utilizing Equation Solving over ‘Big’ Boolean Algebras

2018 ◽  
Vol 3 (4) ◽  
pp. 404-428 ◽  
Author(s):  
Ali Muhammad Ali Rushdi ◽  
Waleed Ahmad
Keyword(s):  
Boolean Algebra ◽  
Circuit Design ◽  
Digital Circuit ◽  
Boolean Algebras ◽  
Binary Vectors ◽  
Equation Solving ◽  
Digital Circuit Design ◽  
Boolean Equation ◽  
Novel Method ◽  
Independent Parameters

A task frequently encountered in digital circuit design is the solution of a two-valued Boolean equation of the form h(X,Y,Z)=1, where h: B_2^(k+m+n)→ B_2 and X,Y, and Z are binary vectors of lengths k, m, and n, representing inputs, intermediary values, and outputs, respectively. The resultant of the suppression of the variables Y from this equation could be written in the form g(X,Z)=1 where g: B_2^(k+n)→ B_2. Typically, one needs to solve for Z in terms of X, and hence it is unavoidable to resort to ‘big’ Boolean algebras which are finite (atomic) Boolean algebras larger than the two-valued Boolean algebra. This is done by reinterpreting the aforementioned g(X,Z) as g(Z): B_(2^K)^n→ B_(2^K ), where B_(2^K ) is the free Boolean algebra FB(X_1,X_2…….X_k ), which has K= 2^k atoms, and 2^K elemnets. This paper describes how to unify many digital specifications into a single Boolean equation, suppress unwanted intermediary variables Y, and solve the equation g(Z)=1 for outputs Z (in terms of inputs X) in the absence of any information about Y. The paper uses a novel method for obtaining the parametric general solutions of the ‘big’ Boolean equation g(Z)=1. The parameters used do not belong to B_(2^K ) but they belong to the two-valued Boolean algebra B_2, also known as the switching algebra or propositional algebra. To achieve this, we have to use distinct independent parameters for each asserted atom in the Boole-Shannon expansion of g(Z). The concepts and methods introduced herein are demonsrated via several detailed examples, which cover the most prominent type among basic problems of digital circuit design.

Digital Circuit Design Challenges and Opportunities in the Era of Nanoscale CMOS

2008 ◽  
Vol 96 (2) ◽  
pp. 343-365 ◽  
Author(s):  
B.H. Calhoun ◽  
Yu Cao ◽  
Xin Li ◽  
Ken Mai ◽  
L.T. Pileggi ◽  
...  
Keyword(s):  
Circuit Design ◽  
Digital Circuit ◽  
Nanoscale Cmos ◽  
Digital Circuit Design ◽  
Challenges And Opportunities ◽  
Design Challenges

Accelerated 3D blind separation of convolved mixtures based on the fast iterative shrinkage thresholding algorithm for adaptive multiple subtraction

Geophysics ◽  
2018 ◽  
Vol 83 (2) ◽  
pp. V99-V113 ◽  
Author(s):  
Zhong-Xiao Li ◽  
Zhen-Chun Li
Keyword(s):  
Field Data ◽  
Optimization Problem ◽  
Computational Cost ◽  
Computation Time ◽  
Blind Separation ◽  
L1 Norm ◽  
Norm Minimization ◽  
Iterative Shrinkage ◽  
Thresholding Algorithm ◽  
Iterative Shrinkage Thresholding

After multiple prediction, adaptive multiple subtraction is essential for the success of multiple removal. The 3D blind separation of convolved mixtures (3D BSCM) method, which is effective in conducting adaptive multiple subtraction, needs to solve an optimization problem containing L1-norm minimization constraints on primaries by the iterative reweighted least-squares (IRLS) algorithm. The 3D BSCM method can better separate primaries and multiples than the 1D/2D BSCM method and the method with energy minimization constraints on primaries. However, the 3D BSCM method has high computational cost because the IRLS algorithm achieves nonquadratic optimization with an LS optimization problem solved in each iteration. In general, it is good to have a faster 3D BSCM method. To improve the adaptability of field data processing, the fast iterative shrinkage thresholding algorithm (FISTA) is introduced into the 3D BSCM method. The proximity operator of FISTA can solve the L1-norm minimization problem efficiently. We demonstrate that our FISTA-based 3D BSCM method achieves similar accuracy of estimating primaries as that of the reference IRLS-based 3D BSCM method. Furthermore, our FISTA-based 3D BSCM method reduces computation time by approximately 60% compared with the reference IRLS-based 3D BSCM method in the synthetic and field data examples.

scholarly journals A Cost-Effective Method for Bulge Prediction in Two Point Incremental Forming

2021 ◽  
Author(s):  
Jaekwang Shin ◽  
Ankush Bansal ◽  
Randy Cheng ◽  
Alan Taub ◽  
Mihaela Banu
Keyword(s):  
Shape Function ◽  
Incremental Forming ◽  
Computational Cost ◽  
Region Of Interest ◽  
Computation Time ◽  
Mesh Size ◽  
Cost Effective ◽  
Summation Method ◽  
Fem Modeling ◽  
Forming Defects

Accurate prediction of the defects occurring in incrementally formed parts has been gaining attention in recent years. This interest is because accurate predictions can overcome the limitation in the advancement of incremental forming in industrial-scale implementation, which has been held back by the increase in the cost and development time due to trial and error methods. The finite element method has been widely utilized to predict the defects in the formed part, e.g., bulge. However, the computation time of running these models and their mesh-size dependency in predicting the forming defects represent barriers in adopting these models as part of CAD-FEM-CAE platforms. Thus, robust analytical and data-driven algorithms must be developed for a cost-effective design of complex parts. In this paper, a new analytical model is proposed to predict the bulge location and geometry in two point incremental forming of an aerospace aluminum alloy AA7075-O for a 67° truncated cone. First, the algorithm calculates the region of interest based on the part geometry. A novel shape function and weighted summation method are then utilized to calculate the amplitude of the instability produced by material accumulation during forming, leading to a bulge on the unformed portion of the sample. It was found that the geometric profile of the part influences the shape function, which is a function created to incorporate the effects of process parameter and boundary condition. The calculated profile in each direction is finalized into one 3-dimensional profile, compared with the experimental results for validation. The proposed model has proven to predict an accurate bulge profile with 95% accuracy comparing with experiments with less than 5% computational cost of FEM modeling.

A MOS Transistor Model for Mixed Analog-digital Circuit Design and Simulation

2006 ◽  
pp. 49-95 ◽  
Author(s):  
Matthias Bucher ◽  
Christophe Lallement ◽  
François Krummenacher ◽  
Christian Enz
Keyword(s):  
Circuit Design ◽  
Digital Circuit ◽  
Mos Transistor ◽  
Digital Circuit Design ◽  
Transistor Model
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