scholarly journals Machine Learning Based Energy-Efficient Design Approach for Interconnects in Circuits and Systems

2021 ◽  
Vol 11 (3) ◽  
pp. 915
Author(s):  
Hung Khac Le ◽  
SoYoung Kim
Keyword(s):  
Energy Efficient ◽  
Power Efficiency ◽  
Microstrip Line ◽  
Supply Voltage ◽  
Low Noise ◽  
Design Flow ◽  
Optimization Process ◽  
Data Generation ◽  
Efficient Design ◽  
Line Design

In this paper, we propose an efficient design methodology for energy-efficient off-chip interconnect. This approach leverages an artificial neural network (ANN) as a surrogate model that significantly improves design efficiency in the frequency-domain. This model utilizes design specifications as the constraint functions to guarantee the satisfaction of design requirements. Additionally, a specified objective function to select low-loss and low-noise structure is employed to determine the optimal case from a large design space. The proposed design flow can find the optimum design that gives maximum eye height (EH) with the largest allowable transmitter supply voltage (VTX) reduction for minimum power consumption. The proposed approach is applied to the microstrip line and stripline structures with single-ended and differential signals for general applicability. For the microstrip line, the proposed methodology performs at a performance speed with 42.7 and 0.5 s per structure for the data generation and optimization process, respectively. In addition, the optimal microstrip line design achieves a 25%VTX reduction. In stripline structures, it takes 31.9 s for the data generation and 0.6 s for the optimization process per structure when the power efficiency reaches a maximum 30.7% peak to peak VTX decrease.

Rotary Coupler in Microstrip Line Design for Data Transmission in the 2.45GHz ISM Band

2020 ◽  
Author(s):  
Benedict Scheiner ◽  
Christopher Beck ◽  
Fabian Lurz ◽  
Martin Frank ◽  
Fabian Michler ◽  
...  
Keyword(s):  
Data Transmission ◽  
Microstrip Line ◽  
Ism Band ◽  
Line Design

Error-aware Design Procedure to Implement Energy-efficient Approximate Squaring Hardware

2020 ◽  
Vol 10 (4) ◽  
pp. 471-477
Author(s):  
Merin Loukrakpam ◽  
Ch. Lison Singh ◽  
Madhuchhanda Choudhury
Keyword(s):  
Energy Saving ◽  
Relative Error ◽  
Energy Efficient ◽  
Piecewise Linear ◽  
Arithmetic Operation ◽  
Design Procedure ◽  
Digital Signal ◽  
Maximum Relative Error ◽  
Square Function ◽  
Efficient Design

Background:: In recent years, there has been a high demand for executing digital signal processing and machine learning applications on energy-constrained devices. Squaring is a vital arithmetic operation used in such applications. Hence, improving the energy efficiency of squaring is crucial. Objective:: In this paper, a novel approximation method based on piecewise linear segmentation of the square function is proposed. Methods: Two-segment, four-segment and eight-segment accurate and energy-efficient 32-bit approximate designs for squaring were implemented using this method. The proposed 2-segment approximate squaring hardware showed 12.5% maximum relative error and delivered up to 55.6% energy saving when compared with state-of-the-art approximate multipliers used for squaring. Results: The proposed 4-segment hardware achieved a maximum relative error of 3.13% with up to 46.5% energy saving. Conclusion:: The proposed 8-segment design emerged as the most accurate squaring hardware with a maximum relative error of 0.78%. The comparison also revealed that the 8-segment design is the most efficient design in terms of error-area-delay-power product.

TRIPLEPR-MAC: A Triple Queue Priority Based Medium Access Control Protocol for Wireless Sensor Network

2019 ◽  
Vol 09 ◽  
Author(s):  
Rinkuben N. Patel ◽  
Nirav V. Bhatt
Keyword(s):  
Sensor Network ◽  
Data Transmission ◽  
Energy Efficient ◽  
Power Efficiency ◽  
Mac Protocol ◽  
Medium Access Control Protocol ◽  
Quality Factors ◽  
Medium Access ◽  
Critical Fields ◽  
Storage Unit

Background: WSN is a network of smart tiny electromechanical devices named as sensors. Sensors perform various tasks like sensing the environment as per its range, transmit the data using transmission units, store the data in the storage unit and perform an action based on captured data. As they are installed in an unfriendly environment, to recharge the sensors are not possible every time which leads to a limited lifetime of a network. To enhance the life of a sensor network, the network required energy-efficient protocols. Various energy-efficient MAC protocols are developed by Research community, but very few of them are integrated with the priority-based environment which performs the priority-based data transmission. Another challenge of WSN is, most of the WSN areas are delay-sensitive because it is implemented in critical fields like military, disaster management, and health monitoring. Energy, Delay, and throughput are major quality factors that affect the sensor network. Objective: In this paper, the aim is to design and develop a MAC Protocol for a field like the military where the system requires energy efficiency and priority-based data transmission. Method: In the proposed model, the cluster-based network with priority queues are formed that can achieve higher power efficiency and less delay for sensitive data. Results: In this research simulation of Proposed MAC, TMAC and SMAC are done with different numbers of nodes, same inter-packet intervals, and variant inter-packet intervals. Based on the script simulation, result graphs are generated. Conclusion: The proposed work achieves greater lifetime compared to TMAC and SMAC using priority-based data transmission.

scholarly journals A High Efficiency Low Noise RF-to-DC Converter Employing Gm-Boosting Envelope Detector and Offset Canceled Latch Comparator

Electronics ◽  
2021 ◽  
Vol 10 (9) ◽  
pp. 1078
Author(s):  
Thi Thuy Pham ◽  
Dongmin Kim ◽  
Seo-Hyeong Jeong ◽  
Junghyup Lee ◽  
Donggu Im
Keyword(s):  
Power Consumption ◽  
High Efficiency ◽  
Supply Voltage ◽  
Current Source ◽  
Low Noise ◽  
The Body ◽  
Common Source ◽  
Conversion Gain ◽  
Input Transistor ◽  
Envelope Detector

This work presents a high efficiency RF-to-DC conversion circuit composed of an LC-CL balun-based Gm-boosting envelope detector, a low noise baseband amplifier, and an offset canceled latch comparator. It was designed to have high sensitivity with low power consumption for wake-up receiver (WuRx) applications. The proposed envelope detector is based on a fully integrated inductively degenerated common-source amplifier with a series gate inductor. The LC-CL balun circuit is merged with the core of the envelope detector by sharing the on-chip gate and source inductors. The proposed technique doubles the transconductance of the input transistor of the envelope detector without any extra power consumption because the gate and source voltage on the input transistor operates in a differential mode. This results in a higher RF-to-DC conversion gain. In order to improve the sensitivity of the wake-up radio, the DC offset of the latch comparator circuit is canceled by controlling the body bias voltage of a pair of differential input transistors through a binary-weighted current source cell. In addition, the hysteresis characteristic is implemented in order to avoid unstable operation by the large noise at the compared signal. The hysteresis window is programmable by changing the channel width of the latch transistor. The low noise baseband amplifier amplifies the output signal of the envelope detector and transfers it into the comparator circuit with low noise. For the 2.4 GHz WuRx, the proposed envelope detector with no external matching components shows the simulated conversion gain of about 16.79 V/V when the input power is around the sensitivity of −60 dBm, and this is 1.7 times higher than that of the conventional envelope detector with the same current and load. The proposed RF-to-DC conversion circuit (WuRx) achieves a sensitivity of about −65.4 dBm based on 45% to 55% duty, dissipating a power of 22 μW from a 1.2 V supply voltage.

scholarly journals A Four-Channel Low-Noise Readout IC for Air Flow Measurement Using Hot Wire Anemometer in 0.18 μm CMOS Technology

Sensors ◽  
2021 ◽  
Vol 21 (14) ◽  
pp. 4694
Author(s):  
Kyeongsik Nam ◽  
Hyungseup Kim ◽  
Yongsu Kwon ◽  
Gyuri Choi ◽  
Taeyup Kim ◽  
...  
Keyword(s):  
Supply Voltage ◽  
Air Flow ◽  
Low Noise ◽  
Cmos Process ◽  
Significant Information ◽  
Flow Measurements ◽  
Pass Filter ◽  
Low Pass Filter ◽  
Op Amp ◽  
Noise Characteristics

Air flow measurements provide significant information required for understanding the characteristics of insect movement. This study proposes a four-channel low-noise readout integrated circuit (IC) in order to measure air flow (air velocity), which can be beneficial to insect biomimetic robot systems that have been studied recently. Instrumentation amplifiers (IAs) with low-noise characteristics in readout ICs are essential because the air flow of an insect’s movement, which is electrically converted using a microelectromechanical systems (MEMS) sensor, generally produces a small signal. The fundamental architecture employed in the readout IC is a three op amp IA, and it accomplishes low-noise characteristics by chopping. Moreover, the readout IC has a four-channel input structure and implements an automatic offset calibration loop (AOCL) for input offset correction. The AOCL based on the binary search logic adjusts the output offset by controlling the input voltage bias generated by the R-2R digital-to-analog converter (DAC). The electrically converted air flow signal is amplified using a three op amp IA, which is passed through a low-pass filter (LPF) for ripple rejection that is generated by chopping, and converted to a digital code by a 12-bit successive approximation register (SAR) analog-to-digital converter (ADC). Furthermore, the readout IC contains a low-dropout (LDO) regulator that enables the supply voltage to drive digital circuits, and a serial peripheral interface (SPI) for digital communication. The readout IC is designed with a 0.18 μm CMOS process and the current consumption is 1.886 mA at 3.3 V supply voltage. The IC has an active area of 6.78 mm2 and input-referred noise (IRN) characteristics of 95.4 nV/√Hz at 1 Hz.

Energy efficient design of building: A review

2012 ◽  
Vol 16 (6) ◽  
pp. 3559-3573 ◽  
Author(s):  
R. Pacheco ◽  
J. Ordóñez ◽  
G. Martínez
Keyword(s):  
Energy Efficient ◽  
Efficient Design ◽  
Energy Efficient Design

A Low-Noise, Low-Power, Wide Dynamic Range Logarithmic Amplifier for Biomedical Applications

2018 ◽  
Vol 27 (07) ◽  
pp. 1850104 ◽  
Author(s):  
Yuwadee Sundarasaradula ◽  
Apinunt Thanachayanont
Keyword(s):  
Low Power ◽  
Biomedical Applications ◽  
Dynamic Range ◽  
Supply Voltage ◽  
Low Noise ◽  
Power Supply Voltage ◽  
Wide Dynamic Range ◽  
Dc Offset ◽  
Limiting Amplifier ◽  
Logarithmic Amplifier

This paper presents the design and realization of a low-noise, low-power, wide dynamic range CMOS logarithmic amplifier for biomedical applications. The proposed amplifier is based on the true piecewise linear function by using progressive-compression parallel-summation architecture. A DC offset cancellation feedback loop is used to prevent output saturation and deteriorated input sensitivity from inherent DC offset voltages. The proposed logarithmic amplifier was designed and fabricated in a standard 0.18[Formula: see text][Formula: see text]m CMOS technology. The prototype chip includes six limiting amplifier stages and an on-chip bias generator, occupying a die area of 0.027[Formula: see text]mm2. The overall circuit consumes 9.75[Formula: see text][Formula: see text]W from a single 1.5[Formula: see text]V power supply voltage. Measured results showed that the prototype logarithmic amplifier exhibited an 80[Formula: see text]dB input dynamic range (from 10[Formula: see text][Formula: see text]V to 100[Formula: see text]mV), a bandwidth of 4[Formula: see text]Hz–10[Formula: see text]kHz, and a total input-referred noise of 5.52[Formula: see text][Formula: see text]V.

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