Optimum Layout of Low Power LC-Based Digitally Controlled Oscillator for Bluetooth Low Energy in a 4G/5G LTE System

This paper presents an optimum layout method of a low-power, digitally controlled oscillator (DCO) for a Bluetooth low-energy (BLE) transceiver in a 4G/5G LTE system. For the optimal LC-based DCO layout, three different layouts, including different gm cell locations and an Al metal layer, were implemented, and performance was compared and verified for BLE application. The implemented neck DCO (NDCO), where the gm cell is located in the neck of the main inductor, showed superior performance compared to other layouts in terms of low phase noise and low power consumption. The designed NDCO had a low phase noise of −116.1 dBc/Hz at 1 MHz with a 0.5 mW power consumption. The supply voltage and oscillation frequency range were 0.8 V and 4.7–5.7 GHz, respectively, and the NDCO designed with the optimal layout had a good figure-of-merit of −192.6 dBc/Hz.

Download Full-text

Hybrid Cross Coupled Differential Pair and Colpitts Quadrature Digitally Controlled Oscillator Architecture

Electronics ◽

10.3390/electronics10101132 ◽

2021 ◽

Vol 10 (10) ◽

pp. 1132

Author(s):

Igor Butryn ◽

Krzysztof Siwiec ◽

Witold Adam Pleskacz

Keyword(s):

Power Consumption ◽

Phase Noise ◽

Output Signal ◽

Communication Systems ◽

Supply Voltage ◽

Hybrid Architecture ◽

Colpitts Oscillator ◽

Digitally Controlled ◽

Differential Pair ◽

Digitally Controlled Oscillator

Growing importance of wireless communication systems forces reduction of power consumption of the designed integrated circuits. The paper focuses on minimization of power consumption in a digitally controlled oscillator (DCO) that can be employed as oscillator in GPS/Galileo receiver. The new hybrid architecture of DCO combines good phase noise performance of a Colpitts oscillator and relaxed startup conditions of a cross-coupled differential pair oscillator. The proposed new DCO generates a quadrature signal in a current reused frequency divider. Such solution allows of the dissipated power to be reduced. The DCO has been implemented in 110 nm CMOS technology. It generates output signal in frequency range from 1.52 GHz to 1.6 GHz and consumes 1.1 mW from 1.5 V supply voltage. The measured phase noise equals −116 dBc/Hz at 1 MHz offset from 1.575 GHz output signal.

Download Full-text

Low Power, Ring VCO with Pre-Charge and Pre-Discharge Circuit for 4 GHz–6.1 GHz Applications in 0.18 μm CMOS

Journal of Circuits System and Computers ◽

10.1142/s0218126619501822 ◽

2019 ◽

Vol 28 (11) ◽

pp. 1950182 ◽

Cited By ~ 1

Author(s):

Nitin Kumar ◽

Manoj Kumar

Keyword(s):

Power Consumption ◽

Low Power ◽

Phase Noise ◽

Supply Voltage ◽

Control Voltage ◽

Cmos Process ◽

Output Frequency ◽

Differential Ring ◽

Low Phase Noise ◽

High Output

The differential ring voltage controlled oscillator (VCO) is one of the critical devices in wireless communication system having excellent stability, controllability and noise rejection ability. A novel design of delay cell is proposed for the four staged CMOS differential ring VCO with high output frequency, low power consumption and low phase noise. The differential ring VCO utilizes multiloop dual delay path topology to acquire both high output frequency and low phase noise. Results have been achieved in TSMC 0.18-[Formula: see text]m CMOS process with a supply voltage ([Formula: see text]) 1.8[Formula: see text]V. The proposed design achieves an output frequency range of 4.029[Formula: see text]GHz to 6.122[Formula: see text]GHz and power of 4.475[Formula: see text]mW is consumed with control voltage variation from 1[Formula: see text]V to 2[Formula: see text]V. The proposed VCO exhibits [Formula: see text]89.7[Formula: see text]dBc/Hz phase noise at 1[Formula: see text]MHz offset frequency and the corresponding figure of merit (FoM) is [Formula: see text]155.9[Formula: see text]dBc/Hz. The design of differential ring VCO with novel delay stage has improved performance in terms of power consumption, output oscillation frequency and phase noise.

Download Full-text

A low-power and low-phase-noise LC digitally controlled oscillator featuring a novel capacitor bank

Journal of Semiconductors ◽

10.1088/1674-4926/31/12/125003 ◽

2010 ◽

Vol 31 (12) ◽

pp. 125003 ◽

Cited By ~ 2

Author(s):

Huanhuan Tian ◽

Zhiqiang Li ◽

Pufeng Chen ◽

Rufei Wu ◽

Haiying Zhang

Keyword(s):

Low Power ◽

Phase Noise ◽

Capacitor Bank ◽

Digitally Controlled ◽

Digitally Controlled Oscillator ◽

Low Phase Noise

Download Full-text

Design of 5 GHz low-power CMOS LC VCO based on complementary cross-coupled topology with modified tail current-shaping technique

International Journal of Microwave and Wireless Technologies ◽

10.1017/s1759078714000300 ◽

2014 ◽

Vol 6 (6) ◽

pp. 573-580 ◽

Cited By ~ 3

Author(s):

Meng-Ting Hsu ◽

Po-Hung Chen ◽

Yao-Yen Lee

Keyword(s):

Power Consumption ◽

Low Power ◽

Phase Noise ◽

Supply Voltage ◽

Voltage Controlled Oscillator ◽

Measurement Results ◽

Low Power Cmos ◽

5 Ghz ◽

Low Phase Noise ◽

Manufacture Company

In this paper, a low-power CMOS LC voltage-controlled oscillator (VCO) with body-biasing and low-phase noise with Q-enhancement techniques is presented. A self-body biased circuit is introduced that can reduce power consumption. Some derivations of the Q-enhancement and how to improve the phase noise of the circuit are also discussed. This chip is implemented by the Taiwan Semiconductor Manufacture Company 0.18 µm 1P6M process. The measurement results exhibit a tuning range of 14.7% from 4.92 to 5.7 GHz at a supply voltage of 1.4 V. The power consumption of the core circuit and figure of merit are 2.5 mW and −188.6 dBc/Hz. The phase noise is −118 dBc/Hz@1 MHz at an operation frequency of 4.94 GHz.

Download Full-text

Low power consumption and low phase noise 2.4 GHz VCO using SiGe HBT for WLL application

Electronics Letters ◽

10.1049/el:19970731 ◽

1997 ◽

Vol 33 (12) ◽

pp. 1089 ◽

Cited By ~ 4

Author(s):

D.-H. Cho ◽

B.R. Ryum ◽

T.-H. Han ◽

S.-M. Lee ◽

K.-W. Yeom ◽

...

Keyword(s):

Power Consumption ◽

Low Power ◽

Phase Noise ◽

Low Power Consumption ◽

Sige Hbt ◽

Low Phase Noise

Download Full-text

A Very Low Power Quadrature VCO with Modified Current-Reuse and Back-Gate Coupling Topology

Journal of Circuits System and Computers ◽

10.1142/s0218126617501845 ◽

2017 ◽

Vol 26 (11) ◽

pp. 1750184 ◽

Cited By ~ 8

Author(s):

Qiuzhen Wan ◽

Jun Dong ◽

Hui Zhou ◽

Fei Yu

Keyword(s):

Power Consumption ◽

Low Power ◽

Phase Noise ◽

Tuning Range ◽

Supply Voltage ◽

Voltage Controlled Oscillator ◽

Back Gate ◽

Current Reuse ◽

Quadrature Vco ◽

In Series

In this paper, a very low power modified current-reused quadrature voltage-controlled oscillator (QVCO) is proposed with the back-gate coupling technique for the quadrature signal generation. By stacking switching transistors in series like a cascode, the modified current-reused QVCO can be constructed in a totem-pole manner to reuse the dc biasing current and lower the power consumption. By utilizing the back-gates of switching transistors as coupling terminals to achieve the quadrature outputs, the back-gate coupled QVCO improves the phase noise and reduces the power consumption compared to the conventional coupling transistor based topology. Together with the modified current-reuse and back-gate coupling techniques, the proposed QVCO can operate at reduced supply voltage and power consumption while maintaining remarkable circuit performance in terms of low phase noise and wide tuning range. With a dc power of 1.6[Formula: see text]mW under a 0.8[Formula: see text]V supply voltage, the simulation results show the tuning range of the QVCO is from 2.36 to 3.04[Formula: see text]GHz as the tuning voltage is varied from 0.8 to 0.0[Formula: see text]V. The phase noise is [Formula: see text]118.3[Formula: see text]dBc/Hz at 1[Formula: see text]MHz offset frequency from the carrier frequency of 2.36[Formula: see text]GHz and the corresponding figure-of-merit of the QVCO is [Formula: see text]183.7[Formula: see text]dBc/Hz.

Download Full-text