scholarly journals Parallel Privacy-Preserving Shortest Path Algorithms

Cryptography ◽  
2021 ◽  
Vol 5 (4) ◽  
pp. 27
Author(s):  
Mohammad Anagreh ◽  
Peeter Laud ◽  
Eero Vainikko
Keyword(s):  
Network Performance ◽  
Transitive Closure ◽  
Control Flow ◽  
Single Instruction Multiple Data ◽  
Multiple Data ◽  
Shortest Distance ◽  
Dense Graphs ◽  
Performance Profiles ◽  
Shortest Path Algorithms ◽  
Memory Accesses

In this paper, we propose and present secure multiparty computation (SMC) protocols for single-source shortest distance (SSSD) and all-pairs shortest distance (APSD) in sparse and dense graphs. Our protocols follow the structure of classical algorithms—Bellman–Ford and Dijkstra for SSSD; Johnson, Floyd–Warshall, and transitive closure for APSD. As the computational platforms offered by SMC protocol sets have performance profiles that differ from typical processors, we had to perform extensive changes to the structure (including their control flow and memory accesses) and the details of these algorithms in order to obtain good performance. We implemented our protocols on top of the secret sharing based protocol set offered by the Sharemind SMC platform, using single-instruction-multiple-data (SIMD) operations as much as possible to reduce the round complexity. We benchmarked our protocols under several different parameters for network performance and compared our performance figures against each other and with ones reported previously.

Towards a Multi Objective Path Optimisation for Car Navigation

2011 ◽  
Vol 65 (1) ◽  
pp. 125-144 ◽  
Author(s):  
Ching-Sheng Chiu ◽  
Chris Rizos
Keyword(s):  
Selection Criteria ◽  
Empirical Studies ◽  
Route Selection ◽  
Multi Objective ◽  
Optimal Paths ◽  
Proposed Model ◽  
Shortest Distance ◽  
Shortest Path Algorithms ◽  
Car Navigation System ◽  
Car Navigation

In a car navigation system the conventional information used to guide drivers in selecting their driving routes typically considers only one criterion, usually the Shortest Distance Path (SDP). However, drivers may apply multiple criteria to decide their driving routes. In this paper, possible route selection criteria together with a Multi Objective Path Optimisation (MOPO) model and algorithms for solving the MOPO problem are proposed. Three types of decision criteria were used to present the characteristics of the proposed model. They relate to the cumulative SDP, passed intersections (Least Node Path – LNP) and number of turns (Minimum Turn Path – MTP). A two-step technique which incorporates shortest path algorithms for solving the MOPO problem was tested. To demonstrate the advantage that the MOPO model provides drivers to assist in route selection, several empirical studies were conducted using two real road networks with different roadway types. With the aid of a Geographic Information System (GIS), drivers can easily and quickly obtain the optimal paths of the MOPO problem, despite the fact that these paths are highly complex and difficult to solve manually.

scholarly journals Investigation of Data Dependencies by Dynamic Analysis of Sapfor

2020 ◽  
Vol 23 (3) ◽  
pp. 473-493
Author(s):  
Nikita Andreevich Kataev ◽  
Alexander Andreevich Smirnov ◽  
Andrey Dmitrievich Zhukov
Keyword(s):  
Dynamic Analysis ◽  
Programming Languages ◽  
Static Analysis ◽  
Automatic Parallelization ◽  
Parallel Execution ◽  
Control Flow ◽  
Analysis Tool ◽  
Data Dependencies ◽  
Program Parallelization ◽  
Memory Accesses

The use of pointers and indirect memory accesses in the program, as well as the complex control flow are some of the main weaknesses of the static analysis of programs. The program properties investigated by this analysis are too conservative to accurately describe program behavior and hence they prevent parallel execution of the program. The application of dynamic analysis allows us to expand the capabilities of semi-automatic parallelization. In the SAPFOR system (System FOR Automated Parallelization), a dynamic analysis tool has been implemented, based on on the instrumentation of the LLVM representation of an analyzed program, which allows the system to explore programs in both C and Fortran programming languages. The capabilities of the static analysis implemented in SAPFOR are used to reduce the overhead program execution, while maintaining the completeness of the analysis. The use of static analysis allows to reduce the number of analyzed memory accesses and to ignore scalar variables, which can be explored in a static way. The developed tool was tested on performance tests from the NAS Parallel Benchmarks package for C and Fortran languages. The implementation of dynamic analysis, in addition to traditional types of data dependencies (flow, anit, output), allows us to determine privitizable variables and a possibility of pipeline execution of loops. Together with the capabilities of DVM and OpenMP these greatly facilitates program parallelization and simplify insertion of the appropriate compiler directives.

scholarly journals abPOA: an SIMD-based C library for fast partial order alignment using adaptive band

2020 ◽  
Author(s):  
Yan Gao ◽  
Yongzhuang Liu ◽  
Yanmei Ma ◽  
Bo Liu ◽  
Yadong Wang ◽  
...  
Keyword(s):  
Error Correction ◽  
Partial Order ◽  
Directed Acyclic Graph ◽  
State Of The Art ◽  
Single Instruction Multiple Data ◽  
Multiple Sequence ◽  
Software Interface ◽  
Multiple Data ◽  
Long Read ◽  
Read Error Correction

AbstractSummaryPartial order alignment, which aligns a sequence to a directed acyclic graph, is now frequently used as a key component in long-read error correction and assembly. We present abPOA (adaptive banded Partial Order Alignment), a Single Instruction Multiple Data (SIMD) based C library for fast partial order alignment using adaptive banded dynamic programming. It can work as a stand-alone multiple sequence alignment and consensus calling tool or be easily integrated into any long-read error correction and assembly workflow. Compared to a state-of-the-art tool (SPOA), abPOA is up to 15 times faster with a comparable alignment accuracy.Availability and implementationabPOA is implemented in C. A stand-alone tool and a C/Python software interface are freely available at https://github.com/yangao07/[email protected] or [email protected]

SIMD (Single Instruction, Multiple Data) Machines

2011 ◽  
pp. 1819-1819
Author(s):  
Jack Dongarra ◽  
Piotr Luszczek ◽  
Felix Wolf ◽  
Jesper Larsson Träff ◽  
Patrice Quinton ◽  
...  
Keyword(s):  
Single Instruction Multiple Data ◽  
Multiple Data

scholarly journals A scalable ASIP for BP Polar decoding with multiple code lengths

2018 ◽  
Vol 232 ◽  
pp. 01046
Author(s):  
Wan Qiao ◽  
Dake Liu
Keyword(s):  
Cmos Technology ◽  
Single Instruction Multiple Data ◽  
Instruction Set ◽  
Maximum Throughput ◽  
Specific Instruction ◽  
Area Efficiency ◽  
Multiple Data ◽  
High Area ◽  
Multiple Code ◽  
Application Specific

In this paper, we propose a flexible scalable BP Polar decoding application-specific instruction set processor (PASIP) that supports multiple code lengths (64 to 4096) and any code rates. High throughputs and sufficient programmability are achieved by the single-instruction-multiple-data (SIMD) based architecture and specially designed Polar decoding acceleration instructions. The synthesis result using 65 nm CMOS technology shows that the total area of PASIP is 2.71 mm2. PASIP provides the maximum throughput of 1563 Mbps (for N = 1024) at the work frequency of 400MHz. The comparison with state-of-art Polar decoders reveals PASIP’s high area efficiency.

scholarly journals A Video Specific Instruction Set Architecture for ASIP design

VLSI Design ◽  
2007 ◽  
Vol 2007 ◽  
pp. 1-7 ◽  
Author(s):  
Zheng Shen ◽  
Hu He ◽  
Yanjun Zhang ◽  
Yihe Sun
Keyword(s):  
Video Coding ◽  
Digital Signal ◽  
Digital Signal Processors ◽  
Single Instruction Multiple Data ◽  
Instruction Set ◽  
Instruction Set Architecture ◽  
Specific Instruction ◽  
Multiple Data ◽  
Signal Processors

This paper describes a novel video specific instruction set architecture for ASIP design. With single instruction multiple data (SIMD) instructions, two destination modes, and video specific instructions, an instruction set architecture is introduced to enhance the performance for video applications. Furthermore, we quantify the improvement on H.263 encoding. In this paper, we evaluate and compare the performance of VS-ISA, other DSPs (digital signal processors), and conventional SIMD media extensions in the context of video coding. Our evaluation results show that VS-ISA improves the processor's performance by approximately 5x on H.263 encoding, and VS-ISA outperforms other architectures by 1.6x to 8.57x in computing IDCT.

Speed improvements of peptide-spectrum matching using Single-Instruction Multiple-Data instructions

PROTEOMICS ◽  
2011 ◽  
Vol 11 (19) ◽  
pp. 3779-3785 ◽  
Author(s):  
Jian Zhang ◽  
Ian McQuillan ◽  
Fang-Xiang Wu
Keyword(s):  
Single Instruction Multiple Data ◽  
Multiple Data ◽  
Spectrum Matching

scholarly journals A High-Performance Parallel FDTD Method Enhanced by Using SSE Instruction Set

2012 ◽  
Vol 2012 ◽  
pp. 1-10 ◽  
Author(s):  
Dau-Chyrh Chang ◽  
Lihong Zhang ◽  
Xiaoling Yang ◽  
Shao-Hsiang Yen ◽  
Wenhua Yu
Keyword(s):  
High Performance ◽  
Fdtd Method ◽  
Hardware Acceleration ◽  
Single Instruction Multiple Data ◽  
Instruction Set ◽  
Computer Cluster ◽  
Simulation Performance ◽  
Acceleration Technique ◽  
Multiple Data ◽  
Difference Time

We introduce a hardware acceleration technique for the parallel finite difference time domain (FDTD) method using the SSE (streaming (single instruction multiple data) SIMD extensions) instruction set. The implementation of SSE instruction set to parallel FDTD method has achieved the significant improvement on the simulation performance. The benchmarks of the SSE acceleration on both the multi-CPU workstation and computer cluster have demonstrated the advantages of (vector arithmetic logic unit) VALU acceleration over GPU acceleration. Several engineering applications are employed to demonstrate the performance of parallel FDTD method enhanced by SSE instruction set.

scholarly journals Energy Effective Congestion Control for Multicast with Network Coding in Wireless Ad Hoc Network

2014 ◽  
Vol 2014 ◽  
pp. 1-12
Author(s):  
Chuanxin Zhao ◽  
Yonglong Luo ◽  
Fulong Chen ◽  
Ji Zhang ◽  
Ruchuan Wang
Keyword(s):  
Energy Consumption ◽  
Congestion Control ◽  
Optimization Design ◽  
Network Performance ◽  
Ad Hoc ◽  
Control Flow ◽  
Network Throughput ◽  
Cross Layer ◽  
Dual Decomposition ◽  
Intermediate Node

In order to improve network throughput and reduce energy consumption, we propose in this paper a cross-layer optimization design that is able to achieve multicast utility maximization and energy consumption minimization. The joint optimization of congestion control and power allocation is formulated to be a nonlinear nonconvex problem. Using dual decomposition, a distributed optimization algorithm is proposed to avoid the congestion by control flow rate at the source node and eliminate the bottleneck by allocating the power at the intermediate node. Simulation results show that the cross-layer algorithm can increase network performance, reduce the energy consumption of wireless nodes and prolong the network lifetime, while keeping network throughput basically unchanged.

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