scholarly journals Technique for Profiling the Cycling-Induced Oxide Trapped Charge in NAND Flash Memories

Electronics ◽  
2021 ◽  
Vol 10 (20) ◽  
pp. 2492
Author(s):  
Yung-Yueh Chiu ◽  
Riichiro Shirota
Keyword(s):  
Flash Memory ◽  
3D Structure ◽  
Tunneling Current ◽  
Nand Flash ◽  
Nand Flash Memory ◽  
Flash Memories ◽  
Testing Procedures ◽  
Physical Measurements ◽  
Endurance Testing ◽  
Increasing Demand

NAND Flash memories have gained tremendous attention owing to the increasing demand for storage capacity. This implies that NAND cells need to scale continuously to maintain the pace of technological evolution. Even though NAND Flash memory technology has evolved from a traditional 2D concept toward a 3D structure, the traditional reliability problems related to the tunnel oxide continue to persist. In this paper, we review several recent techniques for separating the effects of the oxide charge and tunneling current flow on the endurance characteristics, particularly the transconductance reduction (ΔGm,max) statistics. A detailed analysis allows us to obtain a model based on physical measurements that captures the main features of various endurance testing procedures. The investigated phenomena and results could be useful for the development of both conventional and emerging NAND Flash memories.

scholarly journals Temperature Impacts on Endurance and Read Disturbs in Charge-Trap 3D NAND Flash Memories

Micromachines ◽  
2021 ◽  
Vol 12 (10) ◽  
pp. 1152
Author(s):  
Fei Chen ◽  
Bo Chen ◽  
Hongzhe Lin ◽  
Yachen Kong ◽  
Xin Liu ◽  
...  
Keyword(s):  
Flash Memory ◽  
Temperature Effects ◽  
Memory Systems ◽  
Nand Flash ◽  
Nand Flash Memory ◽  
Flash Memories ◽  
Charge Trap ◽  
Fundamental Factor ◽  
Temperature Impacts ◽  
Raw Bit Error Rate

Temperature effects should be well considered when designing flash-based memory systems, because they are a fundamental factor that affect both the performance and the reliability of NAND flash memories. In this work, aiming to comprehensively understanding the temperature effects on 3D NAND flash memory, triple-level-cell (TLC) mode charge-trap (CT) 3D NAND flash memory chips were characterized systematically in a wide temperature range (−30~70 °C), by focusing on the raw bit error rate (RBER) degradation during program/erase (P/E) cycling (endurance) and frequent reading (read disturb). It was observed that (1) the program time showed strong dependences on the temperature and P/E cycles, which could be well fitted by the proposed temperature-dependent cycling program time (TCPT) model; (2) RBER could be suppressed at higher temperatures, while its degradation weakly depended on the temperature, indicating that high-temperature operations would not accelerate the memory cells’ degradation; (3) read disturbs were much more serious at low temperatures, while it helped to recover a part of RBER at high temperatures.

scholarly journals Impact of Residual Stress on a Polysilicon Channel in Scaled 3D NAND Flash Memory

2021 ◽  
Author(s):  
Juyoung Lee ◽  
Dong-Gwan Yoon ◽  
Jae-Min Sim ◽  
Yun-Heub Song
Keyword(s):  
Residual Stress ◽  
Compressive Stress ◽  
Flash Memory ◽  
Computer Aided Design ◽  
Hole Diameter ◽  
Nand Flash ◽  
Nand Flash Memory ◽  
Flash Memories ◽  
Threshold Voltage Shift ◽  
Aided Design

The effects of residual stress in a tungsten gate on a polysilicon channel in scaled 3D NAND flash memories were investigated using a technology computer-aided design simulation. The NAND strings with respect to the distance from the tungsten slit were also analyzed. The scaling of the spacer thickness and hole diameter induced compressive stress on the polysilicon channel. Moreover, the residual stress of polysilicon in the string near the tungsten slit had greater compressive stress than the string farther away. The increase in compressive stress in the polysilicon channel degraded the Bit-Line current (Ion) because of stress-induced electron mobility deterioration. Moreover, a threshold voltage shift (△Vth) occurred in the negative direction because of conduction band lowering.

Flash-Based Storage in Embedded Systems

2013 ◽  
pp. 439-455 ◽  
Author(s):  
Pierre Olivier ◽  
Jalil Boukhobza ◽  
Eric Senn
Keyword(s):  
Embedded Systems ◽  
Flash Memory ◽  
Nand Flash ◽  
Embedded Operating System ◽  
Nand Flash Memory ◽  
Flash Memories ◽  
Software Support ◽  
Average Growth ◽  
Shock Resistance ◽  
Flash Translation Layer

NAND Flash memories gained a solid foothold in the embedded systems domain due to its attractive characteristics in terms of size, weight, shock resistance, power consumption, and data throughput. Moreover, flash memories tend to be less confined to the embedded domain, as it can be observed through the market explosion of flash-based storage systems (average growth of the NVRAM is reported to be about 69% up to 2015). In this chapter, the authors focus on NAND flash memory NVRAM. After a global presentation of its architecture and very specific constraints, they describe the different ways to manage flash memories in embedded systems which are 1) the use of a hardware Flash Translation Layer (FTL), or 2) a dedicated Flash File System (FFS) software support implemented within the embedded operating system kernel.

scholarly journals Impact of Residual Stress on a Polysilicon Channel in Scaled 3D NAND Flash Memory

2021 ◽  
Author(s):  
Juyoung Lee ◽  
Dong-Gwan Yoon ◽  
Jae-Min Sim ◽  
Yun-Heub Song
Keyword(s):  
Residual Stress ◽  
Compressive Stress ◽  
Flash Memory ◽  
Computer Aided Design ◽  
Hole Diameter ◽  
Nand Flash ◽  
Nand Flash Memory ◽  
Flash Memories ◽  
Threshold Voltage Shift ◽  
Aided Design

The effects of residual stress in a tungsten gate on a polysilicon channel in scaled 3D NAND flash memories were investigated using a technology computer-aided design simulation. The NAND strings with respect to the distance from the tungsten slit were also analyzed. The scaling of the spacer thickness and hole diameter induced compressive stress on the polysilicon channel. Moreover, the residual stress of polysilicon in the string near the tungsten slit had greater compressive stress than the string farther away. The increase in compressive stress in the polysilicon channel degraded the Bit-Line current (Ion) because of stress-induced electron mobility deterioration. Moreover, a threshold voltage shift (△Vth) occurred in the negative direction because of conduction band lowering.

Novel Three Dimensional (3D) NAND Flash Memory Array Having Tied Bit-line and Ground Select Transistor (TiGer)

2012 ◽  
Vol E95.C (5) ◽  
pp. 837-841 ◽  
Author(s):  
Se Hwan PARK ◽  
Yoon KIM ◽  
Wandong KIM ◽  
Joo Yun SEO ◽  
Hyungjin KIM ◽  
...  
Keyword(s):  
Flash Memory ◽  
Three Dimensional ◽  
Nand Flash ◽  
Nand Flash Memory ◽  
Memory Array

scholarly journals Artificial Neural Network Assisted Error Correction for MLC NAND Flash Memory

Micromachines ◽  
2021 ◽  
Vol 12 (8) ◽  
pp. 879
Author(s):  
Ruiquan He ◽  
Haihua Hu ◽  
Chunru Xiong ◽  
Guojun Han
Keyword(s):  
Neural Network ◽  
Error Correction ◽  
Error Detection ◽  
Flash Memory ◽  
Nand Flash ◽  
Data Reliability ◽  
Nand Flash Memory ◽  
Process Technology ◽  
Noise Mitigation ◽  
Memory Channel

The multilevel per cell technology and continued scaling down process technology significantly improves the storage density of NAND flash memory but also brings about a challenge in that data reliability degrades due to the serious noise. To ensure the data reliability, many noise mitigation technologies have been proposed. However, they only mitigate one of the noises of the NAND flash memory channel. In this paper, we consider all the main noises and present a novel neural network-assisted error correction (ANNAEC) scheme to increase the reliability of multi-level cell (MLC) NAND flash memory. To avoid using retention time as an input parameter of the neural network, we propose a relative log-likelihood ratio (LLR) to estimate the actual LLR. Then, we transform the bit detection into a clustering problem and propose to employ a neural network to learn the error characteristics of the NAND flash memory channel. Therefore, the trained neural network has optimized performances of bit error detection. Simulation results show that our proposed scheme can significantly improve the performance of the bit error detection and increase the endurance of NAND flash memory.

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