scholarly journals Impact of Residual Stress on a Polysilicon Channel in Scaled 3D NAND Flash Memory

2021 ◽  
Author(s):  
Juyoung Lee ◽  
Dong-Gwan Yoon ◽  
Jae-Min Sim ◽  
Yun-Heub Song
Keyword(s):  
Residual Stress ◽  
Compressive Stress ◽  
Flash Memory ◽  
Computer Aided Design ◽  
Hole Diameter ◽  
Nand Flash ◽  
Nand Flash Memory ◽  
Flash Memories ◽  
Threshold Voltage Shift ◽  
Aided Design

The effects of residual stress in a tungsten gate on a polysilicon channel in scaled 3D NAND flash memories were investigated using a technology computer-aided design simulation. The NAND strings with respect to the distance from the tungsten slit were also analyzed. The scaling of the spacer thickness and hole diameter induced compressive stress on the polysilicon channel. Moreover, the residual stress of polysilicon in the string near the tungsten slit had greater compressive stress than the string farther away. The increase in compressive stress in the polysilicon channel degraded the Bit-Line current (Ion) because of stress-induced electron mobility deterioration. Moreover, a threshold voltage shift (△Vth) occurred in the negative direction because of conduction band lowering.

scholarly journals Impact of Residual Stress on a Polysilicon Channel in Scaled 3D NAND Flash Memory

2021 ◽  
Author(s):  
Juyoung Lee ◽  
Dong-Gwan Yoon ◽  
Jae-Min Sim ◽  
Yun-Heub Song
Keyword(s):  
Residual Stress ◽  
Compressive Stress ◽  
Flash Memory ◽  
Computer Aided Design ◽  
Hole Diameter ◽  
Nand Flash ◽  
Nand Flash Memory ◽  
Flash Memories ◽  
Threshold Voltage Shift ◽  
Aided Design

The effects of residual stress in a tungsten gate on a polysilicon channel in scaled 3D NAND flash memories were investigated using a technology computer-aided design simulation. The NAND strings with respect to the distance from the tungsten slit were also analyzed. The scaling of the spacer thickness and hole diameter induced compressive stress on the polysilicon channel. Moreover, the residual stress of polysilicon in the string near the tungsten slit had greater compressive stress than the string farther away. The increase in compressive stress in the polysilicon channel degraded the Bit-Line current (Ion) because of stress-induced electron mobility deterioration. Moreover, a threshold voltage shift (△Vth) occurred in the negative direction because of conduction band lowering.

scholarly journals A New Read Scheme for Alleviating Cell-to-Cell Interference in Scaled-Down 3D NAND Flash Memory

Electronics ◽  
2020 ◽  
Vol 9 (11) ◽  
pp. 1775
Author(s):  
Jae-Min Sim ◽  
Myounggon Kang ◽  
Yun-Heub Song
Keyword(s):  
Electric Field ◽  
Flash Memory ◽  
Computer Aided Design ◽  
Fundamental Problem ◽  
Adjacent Cell ◽  
Nand Flash ◽  
Nand Flash Memory ◽  
Fundamental Cause ◽  
Tcad Simulation ◽  
Aided Design

In this paper, we investigated the cell-to-cell interference in scaled-down 3D NAND flash memory by using a Technology Computer-Aided Design (TCAD) simulation. The fundamental cause of cell-to-cell interference is that the electric field crowding point is changed by the programmed adjacent cell so that the electric field is not sufficiently directed to the channel surface. Therefore, the channel concentration of the selected cell is changed, leading to a Vth shift. Furthermore, this phenomenon occurs more severely when the selected cell is in an erased state rather than in a programmed state. In addition, it was confirmed that the cell-to-cell interference by the programmed WLn+1 is more severe than that of WLn−1 due to the degradation of the effective mobility effect. To solve this fundamental problem, a new read scheme is proposed. Through TCAD simulation, the cell-to-cell interference was alleviated with a bias having a ΔV of 1.5 V from Vread through an optimization process to have appropriate bias conditions in three ways that are suitable for each pattern. As a result, this scheme narrowed the Vth shift of 67.5% for erased cells and narrowed the Vth shift of 70% for programmed cells. The proposed scheme is one way to solve the cell-to-cell interference that may occur as the cell-to-cell distance decreases for a high stacked 3D NAND structure.

scholarly journals Novel Program Scheme of Vertical NAND Flash Memory for Reduction of Z-Interference

Micromachines ◽  
2021 ◽  
Vol 12 (5) ◽  
pp. 584
Author(s):  
Su-in Yi ◽  
Jungsik Kim
Keyword(s):  
Flash Memory ◽  
Computer Aided Design ◽  
Program Scheme ◽  
Nand Flash ◽  
Nand Flash Memory ◽  
Cell Dimensions ◽  
Computer Aided ◽  
Multi Level ◽  
Aided Design ◽  
Better Than

Minimizing the variation in threshold voltage (Vt) of programmed cells is required to the extreme level for realizing multi-level-cells; as many as even 5 bits per cell recently. In this work, a recent program scheme to write the cells from the top, for instance the 170th layer, to the bottom, the 1st layer, (T-B scheme) in vertical NAND (VNAND) Flash Memory, is investigated to minimize Vt variation by reducing Z-interference. With the aid of Technology Computer Aided Design (TCAD) the Z-Interference for T-B (84 mV) is found to be better than B-T (105 mV). Moreover, under scaled cell dimensions (e.g., Lg: 31→24 nm), the improvement becomes protruding (T-B: 126 mV and B-T: 162 mV), emphasizing the significance of the T-B program scheme for the next generation VNAND products with the higher bit density.

scholarly journals Temperature Impacts on Endurance and Read Disturbs in Charge-Trap 3D NAND Flash Memories

Micromachines ◽  
2021 ◽  
Vol 12 (10) ◽  
pp. 1152
Author(s):  
Fei Chen ◽  
Bo Chen ◽  
Hongzhe Lin ◽  
Yachen Kong ◽  
Xin Liu ◽  
...  
Keyword(s):  
Flash Memory ◽  
Temperature Effects ◽  
Memory Systems ◽  
Nand Flash ◽  
Nand Flash Memory ◽  
Flash Memories ◽  
Charge Trap ◽  
Fundamental Factor ◽  
Temperature Impacts ◽  
Raw Bit Error Rate

Temperature effects should be well considered when designing flash-based memory systems, because they are a fundamental factor that affect both the performance and the reliability of NAND flash memories. In this work, aiming to comprehensively understanding the temperature effects on 3D NAND flash memory, triple-level-cell (TLC) mode charge-trap (CT) 3D NAND flash memory chips were characterized systematically in a wide temperature range (−30~70 °C), by focusing on the raw bit error rate (RBER) degradation during program/erase (P/E) cycling (endurance) and frequent reading (read disturb). It was observed that (1) the program time showed strong dependences on the temperature and P/E cycles, which could be well fitted by the proposed temperature-dependent cycling program time (TCPT) model; (2) RBER could be suppressed at higher temperatures, while its degradation weakly depended on the temperature, indicating that high-temperature operations would not accelerate the memory cells’ degradation; (3) read disturbs were much more serious at low temperatures, while it helped to recover a part of RBER at high temperatures.

Flash-Based Storage in Embedded Systems

2013 ◽  
pp. 439-455 ◽  
Author(s):  
Pierre Olivier ◽  
Jalil Boukhobza ◽  
Eric Senn
Keyword(s):  
Embedded Systems ◽  
Flash Memory ◽  
Nand Flash ◽  
Embedded Operating System ◽  
Nand Flash Memory ◽  
Flash Memories ◽  
Software Support ◽  
Average Growth ◽  
Shock Resistance ◽  
Flash Translation Layer

NAND Flash memories gained a solid foothold in the embedded systems domain due to its attractive characteristics in terms of size, weight, shock resistance, power consumption, and data throughput. Moreover, flash memories tend to be less confined to the embedded domain, as it can be observed through the market explosion of flash-based storage systems (average growth of the NVRAM is reported to be about 69% up to 2015). In this chapter, the authors focus on NAND flash memory NVRAM. After a global presentation of its architecture and very specific constraints, they describe the different ways to manage flash memories in embedded systems which are 1) the use of a hardware Flash Translation Layer (FTL), or 2) a dedicated Flash File System (FFS) software support implemented within the embedded operating system kernel.

scholarly journals Physical and Electrical Analysis of Poly-Si Channel Effect on SONOS Flash Memory

Micromachines ◽  
2021 ◽  
Vol 12 (11) ◽  
pp. 1401
Author(s):  
Jun-Kyo Jeong ◽  
Jae-Young Sung ◽  
Woon-San Ko ◽  
Ki-Ryung Nam ◽  
Hi-Deok Lee ◽  
...  
Keyword(s):  
Flash Memory ◽  
Silicon Oxide ◽  
Memory Performance ◽  
Charge Trapping ◽  
Nand Flash ◽  
Nand Flash Memory ◽  
Data Retention ◽  
Threshold Voltage Shift ◽  
Before And After ◽  
Nitride Oxide

In this study, polycrystalline silicon (poly-Si) is applied to silicon-oxide-nitride-oxide-silicon (SONOS) flash memory as a channel material and the physical and electrical characteristics are analyzed. The results show that the surface roughness of silicon nitride as charge trapping layer (CTL) is enlarged with the number of interface traps and the data retention properties are deteriorated in the device with underlying poly-Si channel which can be serious problem in gate-last 3D NAND flash memory architecture. To improve the memory performance, high pressure deuterium (D2) annealing is suggested as a low-temperature process and the program window and threshold voltage shift in data retention mode is compared before and after the D2 annealing. The suggested curing is found to be effective in improving the device reliability.

scholarly journals Technique for Profiling the Cycling-Induced Oxide Trapped Charge in NAND Flash Memories

Electronics ◽  
2021 ◽  
Vol 10 (20) ◽  
pp. 2492
Author(s):  
Yung-Yueh Chiu ◽  
Riichiro Shirota
Keyword(s):  
Flash Memory ◽  
3D Structure ◽  
Tunneling Current ◽  
Nand Flash ◽  
Nand Flash Memory ◽  
Flash Memories ◽  
Testing Procedures ◽  
Physical Measurements ◽  
Endurance Testing ◽  
Increasing Demand

NAND Flash memories have gained tremendous attention owing to the increasing demand for storage capacity. This implies that NAND cells need to scale continuously to maintain the pace of technological evolution. Even though NAND Flash memory technology has evolved from a traditional 2D concept toward a 3D structure, the traditional reliability problems related to the tunnel oxide continue to persist. In this paper, we review several recent techniques for separating the effects of the oxide charge and tunneling current flow on the endurance characteristics, particularly the transconductance reduction (ΔGm,max) statistics. A detailed analysis allows us to obtain a model based on physical measurements that captures the main features of various endurance testing procedures. The investigated phenomena and results could be useful for the development of both conventional and emerging NAND Flash memories.

Novel Three Dimensional (3D) NAND Flash Memory Array Having Tied Bit-line and Ground Select Transistor (TiGer)

2012 ◽  
Vol E95.C (5) ◽  
pp. 837-841 ◽  
Author(s):  
Se Hwan PARK ◽  
Yoon KIM ◽  
Wandong KIM ◽  
Joo Yun SEO ◽  
Hyungjin KIM ◽  
...  
Keyword(s):  
Flash Memory ◽  
Three Dimensional ◽  
Nand Flash ◽  
Nand Flash Memory ◽  
Memory Array
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