scholarly journals Improving the Performance of the ToGoFET Probe: Advances in Design, Fabrication, and Signal Processing

Micromachines ◽  
2021 ◽  
Vol 12 (11) ◽  
pp. 1303
Author(s):  
Hoontaek Lee ◽  
Junsoo Kim ◽  
Kumjae Shin ◽  
Wonkyu Moon

We report recent improvements of the tip-on-gate of field-effect-transistor (ToGoFET) probe used for capacitive measurement. Probe structure, fabrication, and signal processing were modified. The inbuilt metal-oxide-semiconductor field-effect-transistor (MOSFET) was redesigned to ensure reliable probe operation. Fabrication was based on the standard complementary metal-oxide-semiconductor (CMOS) process, and trench formation and the channel definition were modified. Demodulation of the amplitude-modulated drain current was varied, enhancing the signal-to-noise ratio. The - characteristics of the inbuilt MOSFET reflect the design and fabrication modifications, and measurement of a buried electrode revealed improved ToGoFET imaging performance. The minimum measurable value was enhanced 20-fold.

1987 ◽  
Vol 65 (8) ◽  
pp. 982-986
Author(s):  
J. Marcoux ◽  
J. Orchard-Webb ◽  
J. F. Currie

We report on the fabrication and electrical characterization of a vertical junction-gate field-effect transistor (JFET) that is compatible with all complementary metal oxide semiconductor (CMOS) technologies. It can be used as a buried load for an enhancement n-channel metal oxide semiconductor field-effect transistor (n-MOSFET), replacing the p-MOSFET within the standard CMOS inverter configuration and resulting in a 40% net area economy in standard cells. To be entirely CMOS process compatible, this JFET device differs from others in the literature in that dopant concentrations in the n substrates (1014) and in the p wells (1015) are substantially lower. For integrated-circuit applications, one seeks to use the JFET with the smallest area to minimize parasitic capacitances and to maximize switching speeds. However, at these concentration levels, the dc current–voltage characteristics depend critically on the lateral dimension of the JFET's square channel. Above 10 μm, the characteristics are pentode-like and similar to those of a classic MOSFET. Below 10 μm, the channel is naturally pinched-off, and for reverse gate bias, the small JFETs are triode-like. There is also a nonreciprocity between the source and the drain when the source-to-drain voltage polarity is changed, which is due to the distance between the channel and the electrode collecting the carriers. When its gate is forward-biased, the small JFETs behave as bipolar transistors. Depending on source-to-drain voltage polarities, I–V characteristics exhibit saturation effects caused by base-widening phenomena at the JFET's drain contact.


Crystals ◽  
2019 ◽  
Vol 9 (12) ◽  
pp. 673
Author(s):  
Jing-Jenn Lin ◽  
Ji-Hua Tao ◽  
You-Lin Wu

An organic ferroelectric capacitor, using polyvinylidene difluoride (PVDF) as the dielectric, was fabricated. By connecting the PVDF capacitor in series to the gate of a commercially purchased metal-oxide–semiconductor field-effect transistor (MOSFET), drain current (ID)–drain voltage (VD) characteristics and drain current (ID)–gate voltage (VG) characteristics were measured. In addition, the subthreshold slopes of the MOSFET were determined from the ID–VG curves. It was found that the subthreshold slope could be effectively reduced by 23% of its original value when the PVDF capacitor was added to the gate of the MOSFET.


2021 ◽  
Author(s):  
Kamal Y. Kamal ◽  
Radu Muresan ◽  
Arafat Al-Dweik

<p>This article reviews complementary metal-oxide-semiconductor (CMOS) based physically unclonable functions (PUFs) in terms of types, structures, metrics, and challenges. The article reviews and classifies the most basic PUF types. The article reviews the basic variations originated during a metal–oxide–semiconductor field-effect transistor (MOSFET) fabrication process. Random <a>variations</a> at transistor level lead to acquiring unique properties for electronic chips. These variations help a PUF system to generate a unique response. This article discusses various concepts which allow for more variations at CMOS technology, layout, masking, and design levels. It also discusses various PUF related topics.</p>


1998 ◽  
Vol 37 (Part 1, No. 11) ◽  
pp. 5926-5931
Author(s):  
Masahiro Shimizu ◽  
Takashi Kuroi ◽  
Masahide Inuishi ◽  
Hideaki Arima ◽  
Haruhiko Abe ◽  
...  

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