scholarly journals Integrated Silicon Photonics for Enabling Next-Generation Space Systems

Photonics ◽  
2021 ◽  
Vol 8 (4) ◽  
pp. 131
Author(s):  
George N. Tzintzarov ◽  
Sunil G. Rao ◽  
John D. Cressler
Keyword(s):  
Silicon Photonics ◽  
Radiation Effects ◽  
Space Systems ◽  
Single Event ◽  
Transient Effects ◽  
Single Event Transient ◽  
Space Applications ◽  
Silicon Waveguides ◽  
Current State ◽  
Integrated Silicon Photonics

A review of silicon photonics for space applications is presented. The benefits and advantages of size, weight, power, and cost (SWaP-C) metrics inherent to silicon photonics are summarized. Motivation for their use in optical communications systems and microwave photonics is addressed. The current state of our understanding of radiation effects in silicon photonics is included in this discussion. Total-ionizing dose, displacement damage, and single-event transient effects are discussed in detail for germanium-integrated photodiodes, silicon waveguides, and Mach-Zehnder modulators. Areas needing further study are suggested.

Single-Event Transient Case Study for System-Level Radiation Effects Analysis

2021 ◽  
pp. 1-1
Author(s):  
Michael J. Campola ◽  
Rebekah A. Austin ◽  
Edward P. Wilcox ◽  
Hak S. Kim ◽  
Raymond L. Ladbury ◽  
...  
Keyword(s):  
Radiation Effects ◽  
System Level ◽  
Single Event ◽  
Single Event Transient ◽  
Transient Case

3D numerical simulations of single-event transient effects in SOI FinFETs

2018 ◽  
Vol 17 (4) ◽  
pp. 1608-1614 ◽  
Author(s):  
Zhenyu Wu ◽  
Benneng Zhu ◽  
Tengyue Yi ◽  
Chao Li ◽  
Yi Liu ◽  
...  
Keyword(s):  
Numerical Simulations ◽  
Single Event ◽  
Transient Effects ◽  
Single Event Transient

scholarly journals The Effect of Deep N+ Well on Single-Event Transient in 65 nm Triple-Well NMOSFET

Symmetry ◽  
2019 ◽  
Vol 11 (2) ◽  
pp. 154 ◽  
Author(s):  
Jizuo Zhang ◽  
Jianjun Chen ◽  
Pengcheng Huang ◽  
Shouping Li ◽  
Liang Fang
Keyword(s):  
Integrated Circuit ◽  
Semiconductor Device ◽  
Transient State ◽  
Heavy Ion ◽  
Sensitive Volume ◽  
Substrate Noise ◽  
Single Event ◽  
Transient Effects ◽  
Single Event Transient ◽  
Cosmic Particle

In a triple-well NMOSFET, a deep n+ well (DNW) is buried in the substrate to isolate the substrate noise. The presence of this deep n+ well leads to changes in single-event transient effects compared to bulk NMOSFET. In space, a single cosmic particle can deposit enough charge in the sensitive volume of a semiconductor device to cause a potential change in the transient state, that is, a single-event transient (SET). In this study, a quantitative characterization of the effect of a DNW on a SET in a 65 nm triple-well NMOSFET was performed using heavy ion experiments. Compared with a bulk NMOSFET, the experimental data show that the percentages of average increase of a SET pulse width are 22% (at linear energy transfer (LET) = 37.4 MeV·cm2/mg) and 23% (at LET = 22.2 MeV·cm2/mg) in a triple-well NMOSFET. This study indicates that a triple-well NMOSFET is more sensitive to a SET, which means that it may not be appropriate for radiation hardened integrated circuit design compared with a bulk NMOSFET.

scholarly journals Mitigation and Predictive Assessment of SET Immunity of Digital Logic Circuits for Space Missions

Aerospace ◽  
2020 ◽  
Vol 7 (2) ◽  
pp. 12 ◽  
Author(s):  
Ygor Q. Aguiar ◽  
Frédéric Wrobel ◽  
Jean-Luc Autran ◽  
Paul Leroux ◽  
Frédéric Saigné ◽  
...  
Keyword(s):  
System Integration ◽  
Space Station ◽  
Vlsi Circuits ◽  
Advanced Technology ◽  
Combinational Circuits ◽  
Single Event ◽  
Single Event Transient ◽  
Space Applications ◽  
Predictive Assessment ◽  
Technology Nodes

Due to the intrinsic masking effects of combinational circuits in digital designs, Single-Event Transient (SET) effects were considered irrelevant compared to the data rupture caused by Single-Event Upset (SEU) effects. However, the importance of considering SET in Very-Large-System-Integration (VLSI) circuits increases given the reduction of the transistor dimensions and the logic data path depth in advanced technology nodes. Accordingly, the threat of SET in electronics systems for space applications must be carefully addressed along with the SEU characterization. In this work, a systematic prediction methodology to assess and improve the SET immunity of digital circuits is presented. Further, the applicability to full-custom and cell-based design methodologies are discussed, and an analysis based on signal probability and pin assignment is proposed to achieve a more application-efficient SET-aware optimization of synthesized circuits. For instance, a SET-aware pin assignment can provide a reduction of 37% and 16% on the SET rate of a NOR gate for a Geostationary Orbit (GEO) and the International Space Station (ISS) orbit, respectively.

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