scholarly journals Joint Optimization of Interference Coordination Parameters and Base-Station Density for Energy-Efficient Heterogeneous Networks

Sensors ◽  
2019 ◽  
Vol 19 (9) ◽  
pp. 2154 ◽  
Author(s):  
Yanzan Sun ◽  
Han Xu ◽  
Shunqing Zhang ◽  
Yating Wu ◽  
Tao Wang ◽  
...  

Heterogeneous networks (HetNets), consisting of macro-cells and overlaying pico-cells, have been recognized as a promising paradigm to support the exponential growth of data traffic demands and high network energy efficiency (EE). However, for two-tier heterogeneous architecture deployment of HetNets, the inter-tier interference will be challenging. Time domain further-enhanced inter-cell interference coordination (FeICIC) proposed in 3GPP Release-11 becomes necessary to mitigate the inter-tier interference by applying low power almost blank subframe (ABS) scheme. Therefore, for HetNets deployment in reality, the pico-cell range expansion (CRE) bias, the power of ABS and the density of pico base stations (PBSs) are three important factors for the network EE improvement. Aiming to improve the network EE, the above three factors are jointly considered in this paper. In particular, we first derive the closed-form expression of the network EE as a function of pico CRE bias, power reduction factor of low power ABS and PBS density based on stochastic geometry model. Then, the approximate relationship between pico CRE bias and power reduction factor is deduced, followed by a linear search algorithm to get the near-optimal pico CRE bias and power reduction factor together at a given PBS density. Next, a linear search algorithm is further proposed to optimize PBS density based on fixed pico CRE bias and power reduction factor. Due to the fact that the above pico CRE bias and power reduction factor optimization and PBS density optimization are optimized separately, a heuristic algorithm is further proposed to optimize pico CRE bias, power reduction factor and PBS density jointly to achieve global network EE maximization. Numerical simulation results show that our proposed heuristic algorithm can significantly enhance the network EE while incurring low computational complexity.

Integration ◽  
2017 ◽  
Vol 57 ◽  
pp. 108-124 ◽  
Author(s):  
Mahshid Mojtabavi Naeini ◽  
Sreedharan Baskara Dass ◽  
Chia Yee Ooi ◽  
Tomokazu Yoneda ◽  
Michiko Inoue

Sensors ◽  
2021 ◽  
Vol 21 (18) ◽  
pp. 6111
Author(s):  
Sangjun Lee ◽  
Kyunghwan Cho ◽  
Jihye Kim ◽  
Jongho Park ◽  
Inhwan Lee ◽  
...  

Cryptographic circuits generally are used for applications of wireless sensor networks to ensure security and must be tested in a manufacturing process to guarantee their quality. Therefore, a scan architecture is widely used for testing the circuits in the manufacturing test to improve testability. However, during scan testing, test-power consumption becomes more serious as the number of transistors and the complexity of chips increase. Hence, the scan chain reordering method is widely applied in a low-power architecture because of its ability to achieve high power reduction with a simple architecture. However, achieving a significant power reduction without excessive computational time remains challenging. In this paper, a novel scan correlation-aware scan cluster reordering is proposed to solve this problem. The proposed method uses a new scan correlation-aware clustering in order to place highly correlated scan cells adjacent to each other. The experimental results demonstrate that the proposed method achieves a significant power reduction with a relatively fast computational time compared with previous methods. Therefore, by improving the reliability of cryptography circuits in wireless sensor networks (WSNs) through significant test-power reduction, the proposed method can ensure the security and integrity of information in WSNs.


2020 ◽  
Vol 9 (3) ◽  
pp. 24-38
Author(s):  
Cuong Dinh Tran ◽  
Tam Thanh Dao ◽  
Ve Song Vo

The cuckoo search algorithm (CSA), a new meta-heuristic algorithm based on natural phenomenon of the cuckoo species and Lévy flights random walk has been widely and successfully applied to several optimization problems so far. In the article, two modified versions of CSA, where new solutions are generated using two distributions including Gaussian and Cauchy distributions in addition to imposing bound by best solutions mechanisms are proposed for solving economic load dispatch (ELD) problems with multiple fuel options. The advantages of CSA with Gaussian distribution (CSA-Gauss) and CSA with Cauchy distribution (CSA-Cauchy) over CSA with Lévy distribution and other meta-heuristic are fewer parameters. The proposed CSA methods are tested on two systems with several load cases and obtained results are compared to other methods. The result comparisons have shown that the proposed methods are highly effective for solving ELD problem with multiple fuel options and/nor valve point effect.


2019 ◽  
Vol 24 (11) ◽  
pp. 8443-8465
Author(s):  
Sajjad Rahmanzadeh ◽  
Mir Saman Pishvaee

Sensors ◽  
2018 ◽  
Vol 18 (12) ◽  
pp. 4382 ◽  
Author(s):  
Hany Hussein ◽  
Mohamed Elsayed ◽  
Mahmoud Fakhry ◽  
Usama Sayed Mohamed

Due to the Internet of Things (IoT) requirements for a high-density network with low-cost and low-power physical (PHY) layer design, the low-power budget transceiver systems have drawn momentous attention lately owing to their superior performance enhancement in both energy efficiency and hardware complexity reduction. As the power budget of the classical transceivers is envisioned by using inefficient linear power amplifiers (PAs) at the transmitter (TX) side and by applying high-resolution analog to digital converters (ADCs) at the receiver (RX) side, the transceiver architectures with low-cost PHY layer design (i.e., nonlinear PA at the TX and one-bit ADC at the RX) are mandated to cope with the vast IoT applications. Therefore, in this paper, we propose the orthogonal shaping pulses minimum shift keying (OSP-MSK) as a multiple-input multiple-output (MIMO) modulation/demodulation scheme in order to design the low-cost transceiver architectures associated with the IoT devices. The OSP-MSK fulfills a low-power budget by using constant envelope modulation (CEM) techniques at the TX side, and by applying a low-resolution one-bit ADC at the RX side. Furthermore, the OSP-MSK provides a higher spectral efficiency compared to the recently introduced MIMO-CEM with the one-bit ADC. In this context, the orthogonality between the in-phase and quadrature-phase components of the OSP are exploited to increase the number of transmitted bits per symbol (bps) without the need for extra bandwidth. The performance of the proposed scheme is investigated analytically and via Monte Carlo simulations. For the mathematical analysis, we derive closed-form expressions for assessing the average bit error rate (ABER) performance of the OSP-MSK modulation in conjunction with Rayleigh and Nakagami-m fading channels. Moreover, a closed-form expression for evaluating the power spectral density (PSD) of the proposed scheme is obtained as well. The simulation results corroborate the potency of the conducted analysis by revealing a high consistency with the obtained analytical formulas.


2018 ◽  
Vol 7 (2.7) ◽  
pp. 863
Author(s):  
Damarla Paradhasaradhi ◽  
Kollu Jaya Lakshmi ◽  
Yadavalli Harika ◽  
Busa Ravi Teja Sai ◽  
Golla Jayanth Krishna

In deep sub-micron technologies, high number of transistors is mounted onto a small chip area where, SRAM plays a vital role and is considered as a major part in many VLSI ICs because of its large density of storage and very less access time. Due to the demand of low power applications the design of low power and low voltage memory is a demanding task. In these memories majority of power dissipation depends on leakage power. This paper analyzes the basic 6T SRAM cell operation. Here two different leakage power reduction approaches are introduced to apply for basic 6T SRAM. The performance analysis of basic SRAM cell, SRAM cell using drowsy-cache approach and SRAM cell using clamping diode are designed at 130nm using Mentor Graphics IC Studio tool. The proposed SRAM cell using clamping diode proves to be a better power reduction technique in terms of power as compared with others SRAM structures. At 3.3V, power saving by the proposed SRAM cell is 20% less than associated to basic 6T SRAM Cell.


Sign in / Sign up

Export Citation Format

Share Document