scholarly journals Comparative analysis of SRAM cell with leakage power reduction approaches

2018 ◽  
Vol 7 (2.7) ◽  
pp. 863
Author(s):  
Damarla Paradhasaradhi ◽  
Kollu Jaya Lakshmi ◽  
Yadavalli Harika ◽  
Busa Ravi Teja Sai ◽  
Golla Jayanth Krishna
Keyword(s):  
Low Power ◽  
Power Dissipation ◽  
Low Voltage ◽  
Power Saving ◽  
Vital Role ◽  
Power Reduction ◽  
Leakage Power ◽  
Access Time ◽  
Chip Area ◽  
Sram Cell

In deep sub-micron technologies, high number of transistors is mounted onto a small chip area where, SRAM plays a vital role and is considered as a major part in many VLSI ICs because of its large density of storage and very less access time. Due to the demand of low power applications the design of low power and low voltage memory is a demanding task. In these memories majority of power dissipation depends on leakage power. This paper analyzes the basic 6T SRAM cell operation. Here two different leakage power reduction approaches are introduced to apply for basic 6T SRAM. The performance analysis of basic SRAM cell, SRAM cell using drowsy-cache approach and SRAM cell using clamping diode are designed at 130nm using Mentor Graphics IC Studio tool. The proposed SRAM cell using clamping diode proves to be a better power reduction technique in terms of power as compared with others SRAM structures. At 3.3V, power saving by the proposed SRAM cell is 20% less than associated to basic 6T SRAM Cell.

scholarly journals Design of Low Power Memory Architecture using 10t Sram Array

2019 ◽  
Vol 8 (4) ◽  
pp. 10650-10653
Keyword(s):  
Low Power ◽  
Power Dissipation ◽  
Low Voltage ◽  
Supply Voltage ◽  
Random Access ◽  
Total Power ◽  
Access Time ◽  
Stable Operation ◽  
Sram Cell ◽  
Sram Design

The main aim of electronics is to design low power devices due to the prevalent usage of powered gadget. Ultra low voltage operation of memory cells has become a subject of a lot of interest because of its applications in terribly low energy computing. The stable operation of static random access memory (SRAM) is important for the success of low voltage SRAM and it is achieved by parameter variations of scaled technologies. The power consumption and access time of the SRAM is also a complex parameter due to the unavoidable switching activities of the number of transistors used for different blocks like, SRAM cell, access transistors, pre-charge circuit, sense amplifier and decoders. It has been shown that conventional 6T SRAM fail to achieve low power and delay operation. The proposed 10T SRAM design gives an approach towards the hold power dissipation. The designed circuit has 10 transistors out of that 2 transistors are used as sleep transistor. The sleep transistors are used as switches. Such as header and footer switches and the switches are turned on during active mode of operations and turned off during idle or standby mode of operations. The designed SRAM cell also has conducting pMOS circuit, which can reduces the total power dissipation. The SRAM cell is simulated by using Cadence tool. A supply voltage of 1.8V is used which makes it enough for low power applications. The power obtained as 761.7mW, which reduces 15% of conventional 6T SRAM design. The delay obtained as 125.6ns, which reduces 45% of conventional 6T SRAM.

scholarly journals DESIGN APPROACHES FOR LOW POWER- LOW AREA D FLIP FLOP S IN NANO TECHNOLOGY

2013 ◽  
pp. 231-236
Author(s):  
FAYAZ KHAN ◽  
SIREESH BABU
Keyword(s):  
Low Power ◽  
Power Dissipation ◽  
Vital Role ◽  
Leakage Power ◽  
Total Power ◽  
Short Channel ◽  
Qualitative Comparison ◽  
Flip Flop ◽  
Low Area ◽  
Total Power Consumption

This paper enumerates design of D flip flop with low power and low area for low power applications, for that analysis of various D-flip flops for low power dissipation ,area and delays is carried out at 0.12um to achieve low power, low-area the technology is scaled down to nanometer ranges, due to shrinking process, the leakage power tends to play a vital role in total power consumption at nano meter technology. In this paper, different D flip flop circuits are designed using Berkeley Short Channel Insulated Gate MOSFET (BSIM4) model equations., in this paper to reduce leakage power at 90nm 70nm and 50nm we implement leakage power reduction techniques six techniques are considered they are namely Sleep transistor, sleepy stack, Dual sleep ,Dual stack Forced Transistor sleep (FTS) and Sleepy keeper From the results, it is observed that SLEEP TRANSISTOR, and SLEEPY KEEPER.FORCED TRANSISTOR SLEEP techniques produces lower power dissipation than the other techniques , in this paper a qualitative comparison is done with the help of Dsch,, Micro wind Simulation tools, this paper concludes that a leakage reduction technique produce different power optimization levels for different architectures and employing a suitable technique for a particular architecture will be an effective way of reducing the leakage current and thereby static power.

Design of Low Leakage 9T SRAM Cell with -Low Power Devices

2021 ◽  
pp. 2250027
Author(s):  
Harekrishna Kumar ◽  
V.K Tomar
Keyword(s):  
Low Power ◽  
Supply Voltage ◽  
Schmitt Trigger ◽  
Leakage Power ◽  
Access Time ◽  
Threshold Region ◽  
Large Area ◽  
Transmission Gate ◽  
Low Leakage ◽  
Sram Cell

In this paper, a 9T SRAM cell with low power (LP9T) and improved performance has been proposed. This cell is free from half-select issue and works with single-ended read and differential write operation in the sub-threshold region. To evaluate the relative performance, the obtained characteristics of LP9T SRAM cell are compared with other state-of-the-art designs at 45-nm technology node. The read and write power dissipation of LP9T SRAM cell is reduced by [Formula: see text] and [Formula: see text] as compared to Conv.6T SRAM cell. In proposed cell, leakage power is reduced by [Formula: see text], [Formula: see text], [Formula: see text], [Formula: see text], [Formula: see text] and [Formula: see text] as compared to conventional 6T (Conv.6T), low power (LP8T), transmission gate 8T(TG8T), transmission gate 9T (TG9T), Schmitt trigger 9T (ST9T), and positive feedback control 10T (PFC10T) SRAM cells. This reduction in leakage power is attributed to stacking effect. LP9T SRAM cell also exhibits significant improvement in read/write access time as compared to all considered cells. Also, the read and write energy of proposed cell is lowest among all considered cells. The LP9T SRAM cell has [Formula: see text] and [Formula: see text] higher read and write stability as compared to Conv.6T SRAM cell. Proposed SRAM cell has the highest value of ON to OFF current ratio ([Formula: see text]) which signifies the highest bit-cell density among all considered cells. The LP9T SRAM cell occupies [Formula: see text] large area as compared to Conv.6T SRAM cell. The overall quality of SRAM cell is calculated through the electrical quality metric (EQM). It is observed that LP9T SRAM cell has the highest value of EQM in comparison to considered cells at 0.3[Formula: see text]V supply voltage.

Low Power, High Performance CNTFET-Based SRAM Cell Designs

2020 ◽  
pp. 93-128
Author(s):  
B. K. Madhavi ◽  
Rajendra Prasad Somineni
Keyword(s):  
Low Power ◽  
High Performance ◽  
Scaling Limit ◽  
Cmos Technology ◽  
Leakage Power ◽  
Digital Systems ◽  
Data Retention ◽  
Chip Area ◽  
Reduction Techniques ◽  
Sram Cell

The main objective of this chapter is to provide high-performance, low-power solutions for VLSI system designers. As technology scales down to 32nm and below, the present CMOS technology has to face the scaling limit, such as the increased leakage power, SCEs, and so on. To overcome these limits, the researchers have experimented on other technologies, among which a CNT technology-based device called CNTFET has been evaluated as one of the promising replacements to CMOS technology. In any digital systems, memory is an integral part, and it is also the largest constituent. SRAM is a widely used memory. In today's ICs, SRAM is going to occupy 60-70% of the total chip area. In this connection, this chapter describes the design of CNTFET-based 6T SRAM cell using circuit-level leakage reduction techniques, named sleep transistor, forced stack, data-retention sleep transistor, and stacked sleep.

FPGA Based Low Power ROM Design Using Capacitance Scaling

2014 ◽  
Vol 1082 ◽  
pp. 471-474
Author(s):  
Meenakshi Bansal ◽  
Neha Bansal ◽  
Rishita Saini ◽  
Lakshay Kalra ◽  
Preet Mohan Singh ◽  
...  
Keyword(s):  
Low Power ◽  
Power Dissipation ◽  
Power Saving ◽  
Leakage Power ◽  
Total Power ◽  
Capacitance Scaling

An ideal capacitor will not dissipate any power, but a real capacitor will have some power dissipation. In this work, we are going to design capacitance scaling based low power ROM design. In order to test the compatibility of this ROM design with latest i7 Processor, we are operating this ROM with frequencies (2.9GHz, 3.3GHz, 3.6GHz, 3.8GHz and 4.0GHz) supported by i7 processor.By using different capacitance there comes is reduction in I/O Power and Total power but not in other Powers like Clock, and Leakage (almost negligible). When capacitance goes from 30pF to 5pF, there is a saving of 28.12% occur in I/O Power, saving of 0.2% occur in Leakage Power, there will be a saving of 11.54% occur in Total Power. This design is implemented on Virtex-5 FPGA using Xilinx ISE and Verilog.

scholarly journals Robust 12T Sram Cell Using 45nm Technology

2020 ◽  
pp. 170-174
Author(s):  
N. Geetha Rani ◽  
N. Jyothi ◽  
P. Leelavathi ◽  
P. Deepthi Swarupa Rani ◽  
S. Reshma
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Power Supply ◽  
Power Dissipation ◽  
Supply Voltage ◽  
Leakage Power ◽  
Sram Cell ◽  
Static Power ◽  
Low Supply Voltage ◽  
Multi Core Processor

SRAM cells are used in many applications such as micro and multi core processor. SRAM cell improves both read stability and write ability at low supply voltage. The objective is to reduce the power dissipation of a novel low power 12T SRAM cell. This method removes half-select issue in 6T and 9T SRAM cell. This work proposes new functional low-power designs of SRAM cells with 6T, 9T and 12 transistors which operate at only 0.4V power supply in sub-threshold operation at 45 nm technology. The leakage power consumption of the proposed SRAM cell is thereby reduced compared to that of the conventional six-transistor (6T) SRAM cell. 12T cell obtains low static power dissipation.

Low Voltage Low Power Fully Integrated Chaos Generator

2018 ◽  
Vol 27 (10) ◽  
pp. 1850155 ◽  
Author(s):  
Jie Jin ◽  
LV Zhao
Keyword(s):  
Low Power ◽  
Power Dissipation ◽  
Low Voltage ◽  
Supply Voltage ◽  
Electronic Components ◽  
Ic Design ◽  
Chip Area ◽  
Fully Integrated ◽  
Chaos Generator ◽  
Wide Range

A low voltage low power fully integrated chaos generator is presented in this paper. Comparing with the conventional off-the-shelf electronic components-based chaos generators, the designed circuit is fully integrated, and it achieves lower supply voltage, lower power dissipation and smaller chip area. The proposed fully integrated chaos generator is verified with GlobalFoundries 0.18[Formula: see text][Formula: see text]m CMOS 1P6M RF process using Cadence IC Design Tools. The simulation results demonstrate that the fully integrated chaos generator consumes only 17[Formula: see text]mW from [Formula: see text]2.5[Formula: see text]V supply voltage. Moreover, the chip area of the chaos generator is only 1.755[Formula: see text]mm2 including the testing pads, and it has a wide range of practical application prospects.

scholarly journals Implementation and modeling of low power sleepy stack SRAM cell

2019 ◽  
Vol 2 (1) ◽  
pp. 53-56
Author(s):  
Manvinder Sharma ◽  
Dishant Khosla ◽  
Sohni Singh ◽  
Pankaj Palta
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Leakage Current ◽  
Power Dissipation ◽  
Memory Cell ◽  
Threshold Current ◽  
Heat Emission ◽  
Leakage Power ◽  
Sram Cell ◽  
Future Technologies

for the future technologies in which the devices and circuits are integrating more, low power consuming devices are needed. Mostly the reduction of power dissipation work is concentrated on switching and leakage current. However sub threshold current is also a big factor which leads to power consumption especially for memories. In this paper, leakage power of SRAM memory cell is reduced by power gated sleepy stack structure which leads to lesser power dissipation. The power dissipation is reduced to 226 µW with proposed technique compared with power dissipation of conventional 6T SRAM cell which had 740 µW. With lesser power dissipation the circuit can have more battery backup and lesser heat emission

scholarly journals 9T SRAM CELL WITH MT-SVL TECHNIQUE FOR LEAKAGE POWER REDUCTION

2021 ◽  
Vol 9 (2) ◽  
pp. 1139-1143
Author(s):  
Kothamasu Jyothi, Et. al.
Keyword(s):  
Power Dissipation ◽  
Power Reduction ◽  
Leakage Power ◽  
Voltage Level ◽  
Technology Scaling ◽  
Sram Cell ◽  
Simulation Results ◽  
Leakage Power Dissipation

With the technology scaling there is a decrease in transistor size and increase in number of the transistors per a chip. It causes tremendous increase in complexity and the power dissipation of circuits. This paper mainly focuses on reduction of leakage power dissipation in SRAM 9T cells by employing multi threshold self controllable voltage level circuits  (LSVL & USVL). The Simulation results show that with the employment of MT-SVL technique, leakage power is being reduced compared to the improved SVL technique. The overall simulation is done with CMOS 180nm technology, using the tool of Cadence Virtuoso.

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