scholarly journals Implementation of Word Level Parallel Processing Unfolding Algorithm using VHDL

2019 ◽  
Vol 8 (6) ◽  
pp. 664-667
Keyword(s):  
Parallel Processing ◽  
Impulse Response ◽  
Integrated Circuit ◽  
High Speed ◽  
Finite Impulse Response ◽  
Critical Path ◽  
Experimental Result ◽  
Infinite Impulse Response ◽  
Path Delay ◽  
Iir Filter

Aim of this paper is to apply the unfolding algorithm to FIR (Finite Impulse Response) and IIR (Infinite Impulse Response) filter and compare with original filter and parallel processing filters architecture. FIR filter and IIR filter are implemented by using VHDL (Very High Speed Integrated Circuit Hardware Description Language).In this paper, 2-parallel processing and 3-parallel processing of FIR and IIR filter are implemented and FIR and IIR filter are also implemented with unfolding factor 2 and unfolding factor 3 using VHDL. The simulation is done on Artix-7 series FPGA, target device (xc7a200tfbg676) (speed grade -1) using VIVADO 2016.3. Implemented design works on 1200 KHz clock whereas parallel inputs are generated on 3600 KHz clock. The proposed technique reduces the critical path delay in comparison with existing literature. Also, the experimental result shows that the speed for 3-unfolded IIR filter is more than 3-parallel IIR filter

FPGA-based Implementation of IIR Filter for Real-Time Noise Reduction in Signal

2021 ◽  
Vol 3 (1) ◽  
Author(s):  
Aladin Kapić ◽  
Rijad Sarić ◽  
Slobodan Lubura ◽  
Dejan Jokić
Keyword(s):  
Transfer Function ◽  
Impulse Response ◽  
Discrete Time ◽  
Time Domain ◽  
Digital Filters ◽  
Finite Impulse Response ◽  
Infinite Impulse Response ◽  
Main Role ◽  
Digital Implementation ◽  
Iir Filter

Filtering of unwanted frequencies represents the main aspect of digital signal processing (DSP) in any modern communication system. The main role of the filter is to perform attenuation of certain frequencies and pass only frequencies of interest. In a DSP system, sampled or discrete-time signals are processed by digital filters using different mathematical operations. Digital filters are commonly categorized as Finite Impulse Response (FIR) and Infinite Impulse Response (IIR). This research focuses on the full VHDL implementation of digital second-order lowpass IIR filter for reducing the noisy frequencies on the FPGA board. The initial step is to determine, from continuous time domain function, the transfer function in the complex {s} domain, then map transfer function in complex {z} domain and finally calculate the difference equation in discrete-time domain of the system with adequate coefficients. Prior to the FPGA implementation, the IIR filter is tested in MATLAB using a signal with mixed frequencies and signal with randomly generated noise. The digital implementation is completed by using fixed-point binary vectors and clocked processes.

scholarly journals Comparison of Motion Artefact Reduction Methods and the Implementation of Adaptive Motion Artefact Reduction in Wearable Electrocardiogram Monitoring

Sensors ◽  
2020 ◽  
Vol 20 (5) ◽  
pp. 1468
Author(s):  
Xiang An ◽  
George K. Stylios
Keyword(s):  
Impulse Response ◽  
Adaptive Filter ◽  
Finite Impulse Response ◽  
Median Filter ◽  
Infinite Impulse Response ◽  
Ecg Signal ◽  
Motion Artefact ◽  
Iir Filter ◽  
Adaptive Motion ◽  
Artefact Reduction

A motion artefact is a kind of noise that exists widely in wearable electrocardiogram (ECG) monitoring. Reducing motion artefact is challenging in ECG signal preprocessing because the spectrum of motion artefact usually overlaps with the very important spectral components of the ECG signal. In this paper, the performance of the finite impulse response (FIR) filter, infinite impulse response (IIR) filter, moving average filter, moving median filter, wavelet transform, empirical mode decomposition, and adaptive filter in motion artefact reduction is studied and compared. The results of this study demonstrate that the adaptive filter performs better than other denoising methods, especially in dealing with the abnormal ECG signal which is measured from a patient with heart disease. In the implementation of adaptive motion artefact reduction, the results show that the use of the impedance pneumography signal as the reference input signal for the adaptive filter can effectively reduce the motion artefact in the ECG signal.

scholarly journals Performance Investigation of Digital Lowpass IIR Filter Based on Different Platforms

2021 ◽  
Vol 12 (2) ◽  
pp. 105-111
Author(s):  
Raaed Faleh Hassan
Keyword(s):  
Integrated Circuit ◽  
High Speed ◽  
Filter Design ◽  
Basic Unit ◽  
Infinite Impulse Response ◽  
Design Algorithm ◽  
System Generator ◽  
Iir Filter ◽  
Hardware Description ◽  
And Performance

The work presented in this paper illuminates the design and simulation of a recursive or Infinite Impulse Response (IIR) filter. The proposed design algorithm employs the Genetic Algorithm to determine the filter coefficients to satisfy the required performance. The effectiveness of different platforms on filter design and performance has been studied in this paper. Three different platforms are considered to implement and verify the designed filter’s work through simulation. The first platform is the MATLAB/SIMULINK software package used to implement the Biquad form filter. This technique is the basis for the software implementation of the designed IIR filter. The HDL – Cosimulation technique is considered the second one; it inspired to take advantage of the existing tools in SIMULINK to convert the designed filter algorithm to the Very high-speed integrated circuit Hardware Description Language (VHDL) format. The System Generator is employed as the third technique, in which the designed filter is implemented as a hardware structure based on basic unit blocks provided by Xilinx System Generator. This technique facilitates the implementation of the designed filter in the FPGA target device. Simulation results show that the performance of the designed filter is remarkably reliable even with severe noise levels.

scholarly journals Design and implementation of DA FIR filter for bio-inspired computing architecture

2021 ◽  
Vol 11 (2) ◽  
pp. 1709
Author(s):  
B. U. V. Prashanth ◽  
Mohammed Riyaz Ahmed ◽  
Manjunath R. Kounte
Keyword(s):  
Impulse Response ◽  
Integrated Circuit ◽  
High Speed ◽  
Finite Impulse Response ◽  
Fir Filter ◽  
Optimized Design ◽  
Tightly Coupled ◽  
Hardware Description ◽  
Impulse Response Filter ◽  
Performance Timing

This paper elucidates the system construct of DA-FIR filter optimized for design of distributed arithmetic (DA) finite impulse response (FIR) filter and is based on architecture with tightly coupled co-processor based data processing units. With a series of look-up-table (LUT) accesses in order to emulate multiply and accumulate operations the constructed DA based FIR filter is implemented on FPGA. The very high speed integrated circuit hardware description language (VHDL) is used implement the proposed filter and the design is verified using simulation. This paper discusses two optimization algorithms and resulting optimizations are incorporated into LUT layer and architecture extractions. The proposed method offers an optimized design in the form of offers average miminimizations of the number of LUT, reduction in populated slices and gate minimization for DA-finite impulse response filter. This research paves a direction towards development of bio inspired computing architectures developed without logically intensive operations, obtaining the desired specifications with respect to performance, timing, and reliability.

Research of Sea Clutter Suppression Algorithm Based on GPU

2012 ◽  
Vol 239-240 ◽  
pp. 1194-1201
Author(s):  
Yan Guo ◽  
Shi Dan Li ◽  
De Sheng Wang
Keyword(s):  
Impulse Response ◽  
Finite Impulse Response ◽  
Graphics Processing Unit ◽  
Main Idea ◽  
Fir Filter ◽  
Infinite Impulse Response ◽  
Processing Unit ◽  
Clutter Suppression ◽  
Sea Clutter ◽  
Iir Filter

This paper presents an algorithm of sea clutter suppression using graphics processing unit (GPU) to meet the real-time requirement in the general radar terminal system. The main idea is to convert an infinite impulse response (IIR) filter to a finite impulse response (FIR) filter, which is suitable for the parallelization processing of GPU. Finally, the converted FIR filter algorithm is implemented on the GPU efficiently, achieving a speed approximately twice as fast as that of the previous IIR filter algorithm implemented on the CPU.

scholarly journals A Phasor Measurement Unit Algorithm Using IIR Filters for FPGA Implementation

Electronics ◽  
2019 ◽  
Vol 8 (12) ◽  
pp. 1523
Author(s):  
Cornelis Jan Kikkert
Keyword(s):  
Impulse Response ◽  
Finite Impulse Response ◽  
Block Diagram ◽  
Rate Of Change ◽  
Measurement Unit ◽  
Infinite Impulse Response ◽  
Iir Filters ◽  
Iir Filter ◽  
Phasor Measurement ◽  
Ieee Standard

Phasor measurement units (PMU) are increasingly used in electrical power transmission networks, to maintain stability and protect the network. PMUs accurately measure voltage, phase, frequency, and rate of change of frequency (ROCOF). For reliability, it is desirable to implement a PMU using an FPGA. This paper describes a novel algorithm, suited to implementation in an FPGA and based on a simple PMU block diagram. A description of its realization using low hardware complexity infinite impulse response (IIR) filters is given. The IEC/IEEE standard 60255-118-1:2018 Part 118-1: Synchrophasor measurements for power systems, describes “reference” Finite Impulse Response (FIR) filters for implementing PMU hardware. At the 10 kHz sampling frequency used for our implementation, each “reference” FIR filter requires 100 multipliers, while an 8th order IIR filter only requires 12 multipliers. This paper compares the performance of different order IIR filter-based PMUs with the performance of the same PMU algorithm using the IEC/IEEE FIR reference filter. The IIR-based PMU easily satisfies all the requirements of IEC/IEEE standard and has a much better out of band signal rejection performance than a FIR-based PMU. Steady state errors for a rated voltage ± 10% and a rated frequency ± 5 Hz are < 0.000001% for total vector error (TVE) and < 1 µHz for frequency, with a latency of two mains cycles.

scholarly journals HIGH PERFORMANCE ADAPTIVE FINITE IMPULSE RESPONSE FILTER USING NEW DISTRIBUTED ARITHMETIC ALGORITHM

2017 ◽  
Vol 10 (13) ◽  
pp. 352
Author(s):  
Sandeep Kumar ◽  
Vigneswaran T
Keyword(s):  
Parallel Processing ◽  
Low Power ◽  
Impulse Response ◽  
High Speed ◽  
High Performance ◽  
Finite Impulse Response ◽  
Fir Filter ◽  
Distributed Arithmetic ◽  
Power Filter ◽  
Arithmetic Algorithm

Finite Impulse Response (FIR) filters is very important in signal Processing Applications. This research is to analyze the performance of FIR filter with the Xilinx Software. The Distributed Arithmetic (DA) algorithm is extensively used in FIR Filter to improve its speed and reducing the area of the filter. The design of low power filter will be achieved by pipelining and parallel processing concept on distributed Arithmetic. The aim is to design filter which has less delay time and supports the pipelining/parallel processing feature, helps in high speed with less power dissipation and area. The paper discusses FPGA implementation of FIR filter and due to parallel data processing its computation is fast and also provides an efficient architecture in terms of area and power consumption. New Distributed   Arithmetic is a high performance and for low power filter.

High Speed FIR Filter Using Radix-2r Multiplier and Its Application for Denoising EOG Signal

2021 ◽  
pp. 2150237
Author(s):  
Gundugonti Kishore Kumar ◽  
Balaji Narayanam
Keyword(s):  
High Speed ◽  
Filter Design ◽  
Finite Impulse Response ◽  
Critical Path ◽  
Fir Filter ◽  
Path Delay ◽  
Critical Path Delay ◽  
Filter Architecture ◽  
Constant Multiplication ◽  
Fir Filter Design

In this paper, a modified finite impulse response (FIR) filter design has been proposed for the denoising bio-electrical signals like Electrooculography(EOG). The proposed filter architecture uses modified multiplier block, which is implemented using modified Radix-[Formula: see text] arithmetic-based representation for minimizing the multiple constant multiplication and conventional ripple carry adders are replaced with [Formula: see text] compressors. This proposed architecture is implemented by using Radix-[Formula: see text]-based multiplier and [Formula: see text] compressor architectures for achieving better improvement in the critical path delay. The Radix-[Formula: see text]-based arithmetic bit recording is used in order to reduce the design complexity of the multiplication. The proposed architecture significantly reduced the delay when compared to existing and conventional architectures.

Vibration Suppression Based on Adaptive Feedforward Control With Infinite Impulse Response Filter

2015 ◽  
Author(s):  
Shiying Zhou ◽  
Masayoshi Tomizuka
Keyword(s):  
Impulse Response ◽  
Vibration Suppression ◽  
Finite Impulse Response ◽  
Feedforward Control ◽  
Vibration Signal ◽  
Infinite Impulse Response ◽  
Least Mean Square ◽  
Parameter Adaptation ◽  
Iir Filter ◽  
Adaptive Feedforward

This paper presents adaptive feedforward control for vibration suppression based on an infinite impulse response (IIR) filter structure. The vibration signal and the output signal are available for the algorithm to adaptively update the parameters of the vibration transmission path (VTP) dynamics. Two designs for parameter adaptation are proposed. They provide different methods to get the necessary signals for parameter adaptation of the IIR filter which is different from the conventional finite impulse response (FIR) filter adaptation design. Performance of the proposed designs is compared with the conventional Filtered-x Least Mean Square (FxLMS) method on a hard disk drive (HDD) benchmark problem. The simulation results show that the proposed designs have smaller 3σ value and peak to peak value at steady state.

scholarly journals OPEN CORES FOR DIGITAL SIGNAL PROCESSING

2014 ◽  
Vol 25 (1) ◽  
pp. 53-62
Author(s):  
Juan Camilo Valderrama-Cuervo ◽  
Alexander López-Parrado
Keyword(s):  
Signal Processing ◽  
Digital Signal Processing ◽  
Impulse Response ◽  
Finite Impulse Response ◽  
Digital Signal ◽  
Fir Filter ◽  
Hardware Verification ◽  
Infinite Impulse Response ◽  
Iir Filter ◽  
On Chip

This paper presents the design and implementation of three System-on-Chip (SoC) cores, which implement the Digital Signal Processing (DSP) functions: Finite Impulse Response (FIR) filter, Infinite Impulse Response (IIR) filter and Fast Fourier Transform (FFT). The FIR-filter core is based on the symmetrical realization form, the IIRfilter core is based on the Second Order Sections (SOS) architecture and the FFT core is based on the Radix 22 Single Delay Feedback (R22SDF) architecture. The three cores are compatible with the Wishbone SoC bus, and they were described using generic and structural VHDL. In-system hardware verification was performed by using an OpenRisc-based SoC synthesized on an Altera FPGA. Tests showed that the designed DSP cores are suitable for building SoC based on the OpenRisc processor and the Wishbone bus.

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