Design of PMOS and NMOS Input Folded Cascode Amplifier using 180nm SCL Technology Node for Low Power Application

This paper presents the details design and simulation of the Folded Cascode amplifier using Source-Coupled-Logic (SCL) technology node for both the P-Type Metal Oxide Semiconductor (PMOS) and N-Type Metal Oxide Semiconductor (NMOS) input. The different way to implement the circuit design for a given specification has clearly described including all the design equation has been presented. All the parameter like open loop gain, Unity Gain Bandwidth (UGB) and Phase Margin (PM) are compared for both the NMOS and PMOS input fully differential folded cascode op-amp circuit are discussed and finally we have got after performance analysis that NMOS input fully differential folded cascode op-amp is the best choice for low power high speed application like in pipeline Analog to Digital (ADC). The circuit has been simulated using cadence virtuoso tool in 0.18µm SCL technology node.

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Monolithic 3D (M3D) Complementary Metal-Oxide-Semiconductor (CMOS)-Nano-Electromechanical (NEM) Hybrid Circuits for Low-Power and High-Speed Reconfigurable Logic (RL) Applications

10.7567/ssdm.2016.a-1-01 ◽

2016 ◽

Author(s):

W.Y. Choi

Keyword(s):

Metal Oxide ◽

Low Power ◽

High Speed ◽

Complementary Metal Oxide Semiconductor ◽

Metal Oxide Semiconductor ◽

Oxide Semiconductor ◽

Reconfigurable Logic

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Low power complementary metal‐oxide semiconductor class‐G audio amplifier with gradual power supply switching

IET Circuits Devices & Systems ◽

10.1049/iet-cds.2014.0263 ◽

2015 ◽

Vol 9 (4) ◽

pp. 256-264 ◽

Cited By ~ 2

Author(s):

Bharadvaj Bhamidipati ◽

Adrian I. Colli‐Menchi ◽

Edgar Sánchez‐Sinencio

Keyword(s):

Metal Oxide ◽

Low Power ◽

Power Supply ◽

Complementary Metal Oxide Semiconductor ◽

Metal Oxide Semiconductor ◽

Oxide Semiconductor ◽

Audio Amplifier

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The Effect of Strain on the Formation of Dislocations at the SiGe/Si Interface

MRS Bulletin ◽

10.1557/s0883769400035326 ◽

1996 ◽

Vol 21 (4) ◽

pp. 38-44 ◽

Cited By ~ 62

Author(s):

F.K. LeGoues

Keyword(s):

Metal Oxide ◽

High Speed ◽

High Performance ◽

Field Effect Transistors ◽

Low Cost ◽

Complementary Metal Oxide Semiconductor ◽

Metal Oxide Semiconductor ◽

Oxide Semiconductor ◽

Design Rule ◽

Strained Si

Recently much interest has been devoted to Si-based heteroepitaxy, and in particular, to the SiGe/Si system. This is mostly for economical reasons: Si-based technology is much more advanced, is widely available, and is cheaper than GaAs-based technology. SiGe opens the door to the exciting (and lucrative) area of Si-based high-performance devices, although optical applications are still limited to GaAs-based technology. Strained SiGe layers form the base of heterojunction bipolar transistors (HBTs), which are currently used in commercial high-speed analogue applications. They promise to be low-cost compared to their GaAs counterparts and give comparable performance in the 2-20-GHz regime. More recently we have started to investigate the use of relaxed SiGe layers, which opens the door to a wider range of application and to the use of SiGe in complementary metal oxide semiconductor (CMOS) devices, which comprise strained Si and SiGe layers. Some recent successes include record-breaking low-temperature electron mobility in modulation-doped layers where the mobility was found to be up to 50 times better than standard Si-based metal-oxide-semiconductor field-effect transistors (MOSFETs). Even more recently, SiGe-basedp-type MOSFETS were built with oscillation frequency of up to 50 GHz, which is a new record, in anyp-type material for the same design rule.

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Analysis and Simulation of a Low-Leakage Analog Single Gate and FinFET Circuits

International Journal of Nanoscience ◽

10.1142/s0219581x14500124 ◽

2014 ◽

Vol 13 (02) ◽

pp. 1450012 ◽

Cited By ~ 1

Author(s):

Manorama Chauhan ◽

Ravindra Singh Kushwah ◽

Pavan Shrivastava ◽

Shyam Akashe

Keyword(s):

Integrated Circuits ◽

Metal Oxide ◽

Low Power ◽

High Performance ◽

Complementary Metal Oxide Semiconductor ◽

Metal Oxide Semiconductor ◽

Oxide Semiconductor ◽

Short Channel ◽

State Dependency ◽

Low Leakage

In the world of Integrated Circuits, complementary metal–oxide–semiconductor (CMOS) has lost its ability during scaling beyond 50 nm. Scaling causes severe short channel effects (SCEs) which are difficult to suppress. FinFET devices undertake to replace usual Metal Oxide Semiconductor Field Effect Transistor (MOSFETs) because of their better ability in controlling leakage and diminishing SCEs while delivering a strong drive current. In this paper, we present a relative examination of FinFET with the double gate MOSFET (DGMOSFET) and conventional bulk Si single gate MOSFET (SGMOSFET) by using Cadence Virtuoso simulation tool. Physics-based numerical two-dimensional simulation results for FinFET device, circuit power is presented, and classifying that FinFET technology is an ideal applicant for low power applications. Exclusive FinFET device features resulting from gate–gate coupling are conversed and efficiently exploited for optimal low leakage device design. Design trade-off for FinFET power and performance are suggested for low power and high performance applications. Whole power consumptions of static and dynamic circuits and latches for FinFET device, believing state dependency, show that leakage currents for FinFET circuits are reduced by a factor of over ~ 10X, compared to DGMOSFET and ~ 20X compared with SGMOSFET.

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A Simulation Study of a Gate-All-Around Nanowire Transistor with a Core–Insulator

Micromachines ◽

10.3390/mi11020223 ◽

2020 ◽

Vol 11 (2) ◽

pp. 223 ◽

Cited By ~ 1

Author(s):

Yannan Zhang ◽

Ke Han ◽

and Jiawei Li

Keyword(s):

Metal Oxide ◽

Low Power ◽

Energy Efficient ◽

Field Effect ◽

High Performance ◽

Field Effect Transistors ◽

Future Generation ◽

Metal Oxide Semiconductor ◽

Oxide Semiconductor ◽

Ultra Low Power

Ultra-low power and high-performance logical devices have been the driving force for the continued scaling of complementary metal oxide semiconductor field effect transistors which greatly enable electronic devices such as smart phones to be energy-efficient and portable. In the pursuit of smaller and faster devices, researchers and scientists have worked out a number of ways to further lower the leaking current of MOSFETs (Metal oxide semiconductor field effect transistor). Nanowire structure is now regarded as a promising candidate of future generation of logical devices due to its ultra-low off-state leaking current compares to FinFET. However, the potential of nanowire in terms of off-state current has not been fully discovered. In this article, a novel Core–Insulator Gate-All-Around (CIGAA) nanowire has been proposed, investigated, and simulated comprehensively and systematically based on 3D numerical simulation. Comparisons are carried out between GAA and CIGAA. The new CIGAA structure exhibits low off-state current compares to that of GAA, making it a suitable candidate of future low-power and energy-efficient devices.

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