scholarly journals Urdhva Tiryak Sutra Based Ancient Multiplication in Reversible Logic Circuits

2020 ◽  
Vol 9 (5) ◽  
pp. 685-697
Keyword(s):  
Error Detection ◽  
Power Dissipation ◽  
Digital Circuits ◽  
Vlsi Design ◽  
Logic Circuits ◽  
Arithmetic Logic Unit ◽  
Computation Algorithm ◽  
Speed And Accuracy ◽  
Quantum Parameters ◽  
Logic Unit

The proposed work analyses the employment of an ancient mathematical approach for building an arithmetic logic unit. Dissipation of power is one of the major driving issues in VLSI design. With the assistance of reversible gates, the power dissipation and loss of information can be minimized. The speed and accuracy of the Arithmetic Logic Unit depends on the propagator. Employing the traditional mathematics sutras technique within the computation algorithm reduces the complexity, duration and power. Due to the effect of environmental factors on the digital circuits, parity conserving technique is incorporated for providing error detection ability. The proposed work deal with the design and analysis of 32 bit reversible multiplier using ancient sutras with and without parity conserving technique .The planned work is implemented on Xilinx ISE Spartan 6E series of FPGA and simulation results are obtained. By using Cadence EDA tool, power, area and delay are calculated. The quantum parameters are calculated manually for 32-bit reversible multiplier using ancient technique with and without parity conserving technique using Urdhva Tiryakbhyam sutra.

scholarly journals Design and Implementation of Ternary Logic Circuits for VLSI Applications

2020 ◽  
Vol 9 (4) ◽  
pp. 3117-3121
Keyword(s):  
Power Dissipation ◽  
Digital Circuits ◽  
Propagation Delay ◽  
Logic Circuits ◽  
Combinational Circuits ◽  
Ternary Logic ◽  
Binary Logic ◽  
Design And Implementation ◽  
Half Adder

This paper mainly concentrates on the design and implementation of ternary logic circuits. The ternary numeral system has its base as 3. Ternary logic will use three symbols, which are, 0,1 and 2. The ternary logic has significant merits over binary logic in designing digital circuits. In this paper, it is proposed to implement a half adder circuit using ternary 3 to 1 multiplexer. The main objective of the work is, to design and implement ternary logic circuits and to analyse the function of the ternary combinational circuits using mentor graphics tool in 90nm technology. This paper also compares the ternary half adder design using k-map method with the proposed ternary half adder using multiplexer in terms of power dissipation, propagation delay and transistor count

Performance Analysis of Wide AND OR Structures Using Keeper Architectures in Various Complementary Metal Oxide Semiconductors Technologies

2016 ◽  
Vol 13 (10) ◽  
pp. 6999-7008
Author(s):  
N Anusha ◽  
T Sasilatha
Keyword(s):  
Comparative Analysis ◽  
Performance Analysis ◽  
Metal Oxide ◽  
Leakage Current ◽  
Power Dissipation ◽  
Vlsi Design ◽  
Logic Circuits ◽  
Cmos Circuits ◽  
Oxide Semiconductors ◽  
Dynamic Circuits

Power dissipation and area are the important constraints in VLSI design. Various techniques are employed in reducing the power dissipation of the logic circuits. Dynamic CMOS circuits are one of the techniques in VLSI to lower the power dissipation. All gates can be designed using dynamic CMOS to lower the power dissipation. In this paper wide AND OR gates are implemented using Dynamic circuits, where keeper architecture is employed in order to prevent leakage current and to ensure that correct output is obtained. The performance analysis of Wide AND OR structures implemented in dynamic CMOS with mandatory keeper architectures in ultra submicron range are analyzed. A comparative analysis of Power dissipation and area of the keeper architectures employed in dynamic CMOS in different lower nanometer such as 120 nm, 90 nm, 70 nm and 50 nm is analyzed.

Design of a New Parity Preserving Reversible Full Adder

2014 ◽  
Vol 24 (01) ◽  
pp. 1550006 ◽  
Author(s):  
Majid Haghparast ◽  
Soghra Shoaei
Keyword(s):  
Fault Tolerance ◽  
Power Consumption ◽  
Error Detection ◽  
Power Dissipation ◽  
Vlsi Design ◽  
Full Adder ◽  
Digital Systems ◽  
The Other ◽  
Optimum Number ◽  
Quantum Cost

Power dissipation is one of the important issues in VLSI design. Reversible logic has zero power dissipation; therefore, nowadays, researchers attend to it in order to optimize the internal power consumption. On the other hand, fault tolerance is a solution for error detection in digital systems. In many systems, fault tolerance is achieved by parity checking. This article proposes a new parity-preserving reversible full adder circuit. For many years, researchers assumed that the quantum cost (QC) of the parity-preserving reversible full adder is 11. In this article we offered a new parity-preserving reversible full adder circuit with a QC of only 9. In addition, the proposed parity-preserving reversible full adder has optimum number of constant inputs and garbage outputs. A novel parity-preserving reversible 4:2 compressor circuit is also proposed using the proposed parity-preserving reversible full adder. This article would be a great initiation for building more complex parity-preserving reversible circuits. All the scales are in the nanometric area, and their fundamental parts are no bigger than a few nanometers.

Comparative Analysis of CNTFET and CMOS Logic based Arithmetic Logic Unit

2017 ◽  
Vol 9 (4) ◽  
pp. 04018-1-04018-4
Author(s):  
K. Nehru ◽  
◽  
T. Nagarjuna ◽  
G. Vijay ◽  
◽  
...  
Keyword(s):  
Comparative Analysis ◽  
Arithmetic Logic Unit ◽  
Logic Unit

Improving Performance of a Multi-Bit Arithmetic Logic Unit

2021 ◽  
Vol 26 (1) ◽  
pp. 40-53
Author(s):  
A.N. Yakunin ◽  
◽  
Aung Myo San ◽  
Khant Win ◽  
◽  
...  
Keyword(s):  
High Speed ◽  
Operating Time ◽  
Arithmetic Logic Unit ◽  
Maximum Delay ◽  
Sequential Organization ◽  
Quartus Ii ◽  
Logic Unit

In modern microprocessors to reduce the time resources the arithmetic-logic units (ALU) with an increased organization of arithmetic carry, characterized by high speed, compared to ALU with sequential organization of the arithmetic carry, are commonly used. However, while increasing the bit number of the input operands, the operating time of ALU of ALU with the accelerated arithmetic carry increases linearly depending on the number of bits. Therefore, the development of ALU, providing higher performance than the existing known solutions, is an actual task. In this work the analysis of ALU with sequential and accelerated organization of the arithmetic carry has been performed. To increase the speed of the operation, a multi-bit ALU has been developed. The simulation of ALU circuits has been executed in Altera Quartus –II CAD environment. The comparison has been performed by the number of logical elements and the maximum delay as a result of modeling the ALU circuits for 4, 8, 16, 32, and 64 bits. A scheme for checking the results has been implemented to confirm the reliability of developed ALU. As a result, it has been found that when performing operations with the 64-bit operands, the developed ALU reduces the maximum delay by 53 % compared to ALU with sequential arithmetic carry and by 35.5 % compared to ALU with the accelerated arithmetic carry, respectively.

New structures of the concurrent error detection systems for logic circuits

2017 ◽  
Vol 78 (2) ◽  
pp. 300-312 ◽  
Author(s):  
V. V. Sapozhnikov ◽  
Vl. V. Sapozhnikov ◽  
D. V. Efanov ◽  
V. V. Dmitriev
Keyword(s):  
Error Detection ◽  
Logic Circuits ◽  
Concurrent Error Detection ◽  
Detection Systems

scholarly journals ECL-Based SiC Logic Circuits for Extreme Temperatures

2015 ◽  
Vol 821-823 ◽  
pp. 910-913 ◽  
Author(s):  
Luigia Lanni ◽  
Bengt Gunnar Malm ◽  
Mikael Östling ◽  
Carl Mikael Zetterling
Keyword(s):  
Power Consumption ◽  
Oscillation Frequency ◽  
Digital Circuits ◽  
Supply Voltage ◽  
Logic Circuits ◽  
Ring Oscillator ◽  
Extreme Temperatures ◽  
Temperature Range ◽  
Stable Noise ◽  
Gate Design

Integrated digital circuits, fabricated in a bipolar SiC technology, have been successfully tested up to 600 °C. Operated with-15 V supply voltage from 27 up to 600 °C OR-NOR gates exhibit stable noise margins of about 1 or 1.5 V depending on the gate design, and increasing delay-power consumption product in the range 100 - 200 nJ. In the same temperature range an oscillation frequency of about 1 MHz is also reported for an 11-stage ring oscillator.

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