scholarly journals FDTD modeling for Crosstalk Reduction in Coupled RLC Interconnects with Active Shielding

2019 ◽  
Vol 8 (11) ◽  
pp. 1038-1042
Keyword(s):  
Crosstalk Noise ◽  
Delay Reduction ◽  
Proposed Model ◽  
Rlc Interconnects ◽  
Crosstalk Reduction ◽  
Global Interconnects ◽  
Active Shielding

This paper presents efficient geometry for crosstalk noise and delay reduction using Active shielding in RLC interconnects with resistive drivers .FDTD modeling has been used for proposed geometry and is validated by HSPICE simulations for 32nm global interconnects .From the results it has been verified that the proposed model results and HSPICE simulations differ by 5% . From the outcomes it has been confirmed that the proposed model outcomes and HSPICE outcomes differ by 5% and by using proposed geometry crosstalk noise and delay has come down by 73% and 60% when compared to unshielded line

scholarly journals FDTD Modeling with Passive Shielding for Crosstalk Reduction in Coupled RLC Interconnects

2019 ◽  
Vol 8 (3) ◽  
pp. 4965-4970
Keyword(s):  
Crosstalk Noise ◽  
Worst Case ◽  
Delay Reduction ◽  
Proposed Model ◽  
Rlc Interconnects ◽  
Crosstalk Reduction ◽  
Global Interconnects

This paper presents passive shielding technique for crosstalk noise and delay reduction in resistive driven RLC interconnect. FDTD technique is used for modeling proposed geometry. The worst case delay and noise induced due to crosstalk in passive shielded interconnects are compared with unshielded lines and is validated using HSPICE simulations for 32nm global interconnects. From the results it has been demonstrated that the proposed model results and HSPICE simulations differ by 8% and by using proposed geometry crosstalk noise and delay has come down by 90% and 52% when compared to unshielded line.

Geometry Induced Crosstalk Reduction in CNT Interconnects for VLSI Circuits

2018 ◽  
Vol 24 (8) ◽  
pp. 5778-5784
Author(s):  
P. Uma Sathyakam ◽  
Paridhi Singh ◽  
Priyamanga Bhardwaj ◽  
P. S Mallick
Keyword(s):  
Carbon Nanotube ◽  
Transmission Line ◽  
Vlsi Circuits ◽  
Delay Reduction ◽  
Capacitively Coupled ◽  
Coupling Capacitance ◽  
Crosstalk Reduction ◽  
Global Interconnects ◽  
Transmission Line Models

This paper proposes novel triangular cross sectioned geometry of carbon nanotube (CNT) bundles for crosstalk and hence, delay reduction in CNT bundle interconnects for VLSI circuits. We formulate the equivalent single conductor (ESC) transmission line models of the interconnects and show that the coupling capacitance of triangular bundle is 29% lesser than the traditionally used square bundles of carbon nanotube interconnects. We further simulate the proposed ESC models of capacitively coupled CNT bundle interconnects using Smart SPICE and find that the crosstalk induced delay of triangular interconnects is 30% lesser as compared to square bundle interconnects. The reduction in delay is found to increase as the number of CNTs increase in the bundle. From these results, we suggest that triangle cross-sectioned CNT bundles are the most suitable candidates as global interconnects.

Geometry-Based Crosstalk Reduction in CNT Interconnects

2019 ◽  
Vol 29 (06) ◽  
pp. 2050094 ◽  
Author(s):  
P. Uma Sathyakam ◽  
P. S. Mallick ◽  
Paridhi Singh
Keyword(s):  
Carbon Nanotube ◽  
Transmission Line ◽  
Vlsi Circuits ◽  
Delay Reduction ◽  
Capacitively Coupled ◽  
Coupling Capacitance ◽  
Propagation Delays ◽  
Crosstalk Reduction ◽  
Global Interconnects ◽  
Transmission Line Models

This paper proposes novel triangular cross-sectioned geometry of carbon nanotube (CNT) bundles for crosstalk and delay reduction in CNT bundle interconnects for VLSI circuits. First, we formulate the equivalent single conductor (ESC) transmission line models of the interconnects. Through SPICE analysis of the ESC circuits, we find the propagation delays of the proposed CNT bundles. Next, we model the capacitively coupled interconnects for crosstalk analysis. It is found that the coupling capacitance of triangular CNT bundle is 29% lesser than the traditionally used square CNT bundles. Further, the crosstalk-induced delay of triangular interconnects is found to be 30% lesser when compared to square bundle interconnects. The reduction in delay is found to increase as the number of CNTs in the bundle increases. So, we suggest that triangular CNT bundles are the most suitable candidates as global interconnects.

ACCURATE ANALYSIS OF GLOBAL INTERCONNECTS IN NANO-FPGAs

NANO ◽  
2009 ◽  
Vol 04 (03) ◽  
pp. 171-176 ◽  
Author(s):  
DAVOOD FATHI ◽  
BEHJAT FOROUZANDEH
Keyword(s):  
Propagation Delay ◽  
Modeling Method ◽  
Accurate Analysis ◽  
Proposed Model ◽  
Simulation Results ◽  
The Difference ◽  
A New Technique ◽  
Global Interconnects ◽  
Technology Nodes ◽  
Model Technique

This paper introduces a new technique for analyzing the behavior of global interconnects in FPGAs, for nanoscale technologies. Using this new enhanced modeling method, new enhanced accurate expressions for calculating the propagation delay of global interconnects in nano-FPGAs have been derived. In order to verify the proposed model, we have performed the delay simulations in 45 nm, 65 nm, 90 nm, and 130 nm technology nodes, with our modeling method and the conventional Pi-model technique. Then, the results obtained from these two methods have been compared with HSPICE simulation results. The obtained results show a better match in the propagation delay computations for global interconnects between our proposed model and HSPICE simulations, with respect to the conventional techniques such as Pi-model. According to the obtained results, the difference between our model and HSPICE simulations in the mentioned technology nodes is (0.29–22.92)%, whereas this difference is (11.13–38.29)% for another model.

A novel MRTD model for signal integrity analysis of resistive driven coupled copper interconnects

2018 ◽  
Vol 37 (1) ◽  
pp. 189-207
Author(s):  
Shashank Rebelli ◽  
Bheema Rao Nistala
Keyword(s):  
Time Domain ◽  
Integrated Circuit ◽  
Signal Integrity ◽  
Propagation Delay ◽  
Average Error ◽  
Crosstalk Noise ◽  
Content Type ◽  
Proposed Model ◽  
On Chip ◽  
Coupling Parasitics

Purpose This paper aims to model the coupled on-chip Copper (Cu) interconnects by using the multiresolution time-domain (MRTD) method. Design/methodology/approach The proposed model is a wavelet-based numerical method for analyzing signal integrity and propagation delay of coupled on-chip interconnects. Moreover, the dependency of crosstalk noise and delay on coupling parasitics (L12, C12) are analyzed. Findings The proposed MRTD method captures the behaviour of propagation delay and peak crosstalk noise on victim line against coupling parasitics, which is in close agreement with that of H simulation program with integrated circuit emphasis (HSPICE). The average error for the proposed model is less than 1 per cent with respect to HSPICE for the estimation of peak crosstalk noise voltage. Practical implications Simulations are performed using HSPICE and compared with those performed using the proposed MRTD method for global interconnect length with 130-nm technology, where the computations of the proposed model are carried out using Matlab. Originality/value The MRTD method with its unique features is tailored for modelling interconnects. To build further credence to this and its profound existence in the latest state-of-art works, simulations of crosstalk noise and propagation delay, for coupled Cu interconnect lines, using MRTD and finite-difference time-domain (FDTD) are executed. The results illustrated the dominance of MRTD method over FDTD in terms of accuracy.

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