A novel MRTD model for signal integrity analysis of resistive driven coupled copper interconnects

2018 ◽  
Vol 37 (1) ◽  
pp. 189-207
Author(s):  
Shashank Rebelli ◽  
Bheema Rao Nistala
Keyword(s):  
Time Domain ◽  
Integrated Circuit ◽  
Signal Integrity ◽  
Propagation Delay ◽  
Average Error ◽  
Crosstalk Noise ◽  
Content Type ◽  
Proposed Model ◽  
On Chip ◽  
Coupling Parasitics

Purpose This paper aims to model the coupled on-chip Copper (Cu) interconnects by using the multiresolution time-domain (MRTD) method. Design/methodology/approach The proposed model is a wavelet-based numerical method for analyzing signal integrity and propagation delay of coupled on-chip interconnects. Moreover, the dependency of crosstalk noise and delay on coupling parasitics (L12, C12) are analyzed. Findings The proposed MRTD method captures the behaviour of propagation delay and peak crosstalk noise on victim line against coupling parasitics, which is in close agreement with that of H simulation program with integrated circuit emphasis (HSPICE). The average error for the proposed model is less than 1 per cent with respect to HSPICE for the estimation of peak crosstalk noise voltage. Practical implications Simulations are performed using HSPICE and compared with those performed using the proposed MRTD method for global interconnect length with 130-nm technology, where the computations of the proposed model are carried out using Matlab. Originality/value The MRTD method with its unique features is tailored for modelling interconnects. To build further credence to this and its profound existence in the latest state-of-art works, simulations of crosstalk noise and propagation delay, for coupled Cu interconnect lines, using MRTD and finite-difference time-domain (FDTD) are executed. The results illustrated the dominance of MRTD method over FDTD in terms of accuracy.

Delay model for dynamically switching coupled on-chip interconnects

2014 ◽  
Vol 12 (3) ◽  
pp. 364-373
Author(s):  
Devendra Kumar Sharma ◽  
Brajesh Kumar Kaushik ◽  
R.K. Sharma
Keyword(s):  
Analytical Model ◽  
Propagation Delay ◽  
Average Error ◽  
Delay Model ◽  
Content Type ◽  
Phase Switching ◽  
Capacitively Coupled ◽  
Interconnect Delay ◽  
Proposed Model ◽  
On Chip

Purpose – The purpose of this paper is to propose an analytical model for estimating propagation delay in coupled resistance-inductance-capacitance (RLC) interconnects. Design/methodology/approach – With higher frequency of operation, longer length of interconnect and fast transition time of the signal, the resistor capacitor (RC) models are not sufficient to estimate the delay accurately. To mitigate this problem, accurate delay models for coupled interconnects are required. In this paper, an analytical model for estimation of interconnect delay is developed for simultaneously switching lines. Two distributed RLC lines coupled inductively and capacitively are considered. To validate the proposed model, SPICE results are compared with the proposed analytical results. Each line in the coupled structure is terminated by a capacitive load of 30fF. The driving signal is considered symmetrical with equal rise and fall time of 5 ps and OFF/ON time of 45 ps. The model is validated for both in-phase and out of phase switching of lines. Findings – It is observed that the model works well for both the phases of inputs switching. The derived expressions of delay exhibit complete physical insight, and the results obtained are in excellent agreement with SPICE results. Comparison of analytical delay with SPICE delay shows an average error of < 2.7 per cent. Originality/value – The analytical expressions for interconnect delay are derived for the first time under simultaneously switching scenario. This model is useful to estimate delay across the inductively and capacitively coupled interconnects.

Crosstalk Noise Analysis in Coupled On-Chip Interconnects Using MRTD Technique

2021 ◽  
Author(s):  
Bhaskar Gugulothu ◽  
Rajendra Naik Bhukya
Keyword(s):  
Time Domain ◽  
Electromagnetic Compatibility ◽  
Noise Analysis ◽  
Fdtd Method ◽  
Average Error ◽  
Propagation Time ◽  
Crosstalk Noise ◽  
Peak Voltage ◽  
Proposed Model ◽  
On Chip

Abstract In this paper, the Crosstalk noise analysis of coupled on-chip interconnects have been analyzed. The multiresolution time-domain method (MRTD) is used to analyze the crosstalk noise model. The crosstalk induced propagation time delay and crosstalk peak voltage on the victim line of interconnects have been determined and compared to those of the conventional finite difference time domain (FDTD) method and validated with HSPICE simulations at the 22nm technology node. The results of the proposed method shows that crosstalk induced propagation delay in dynamic in-phase, out-phase and peak voltage timing, as well as the peak voltage value for functional crosstalk in the copper interconnects are an average error of less than 0.53% for the proposed model and HSPICE simulations. The results of the proposed model are closely similar to those of HSPICE simulations. Electromagnetic interference and electromagnetic compatibility of on-chip interconnects can also be addressed using the proposed method.

Impact of driver size and interwire parasitics on crosstalk noise and delay

2014 ◽  
Vol 12 (4) ◽  
pp. 475-490
Author(s):  
Devendra Kumar Sharma ◽  
Brajesh Kumar Kaushik ◽  
R.K. Sharma
Keyword(s):  
Integrated Circuit ◽  
Large Scale ◽  
Propagation Delay ◽  
Combined Effects ◽  
Crosstalk Noise ◽  
Content Type ◽  
Coupling Capacitance ◽  
Large Scale Integration ◽  
Scale Integration ◽  
Coupling Parasitics

Purpose – The purpose of this research paper is to analyze the combined effects of driver size and coupling parasitics on crosstalk noise and delay for static and dynamically switching victim line. Furthermore, this paper shows the effect of inductance on delay and qualitatively optimizes its value to obtain minimum delay. Design/methodology/approach – The interwire parasitics are the primary sources of crosstalk or coupled noise that may lead to critical delays/logic malfunctions. This paper is based on simulating a pair of distributed resistance inductance capacitance (RLC) interconnects coupled capacitively and inductively for measurements of crosstalk noise/delay. The combined effects of driver sizing and interwire parasitics on peak overshoot noise/delay are observed through simulation program with integrated circuit emphasis (SPICE) simulations for different switching patterns. Furthermore, the analysis of inductive effect on propagation delay as a function of coupling capacitance is carried out and the optimization of delay is worked out qualitatively. The simulations are carried out at 0.13 μm, 1.5 V technology node. Findings – This paper observes the contradictory effects of coupling parasitics on wire propagation delay; however, the effect on peak noise is of a different kind. Further, this paper shows that the driver size exhibits opposite kind of behavior on propagation delay than peak over shoot noise. It is observed that the delay is affected in presence of inductance; thus, the optimization of delay is carried out. Originality/value – The effects of driver sizing and interwire parasitics are analyzed through simulations. The optimum value of coupling capacitance for delay is found qualitatively. These findings are important for designing very large scale integration (VLSI) interconnects.

scholarly journals TRANSIENT RESPONSE OF A DISTRIBUTED RLC INTERCONNECT BASED ON DIRECT POLE EXTRACTION

2009 ◽  
Vol 18 (07) ◽  
pp. 1263-1285 ◽  
Author(s):  
GUOQING CHEN ◽  
EBY G. FRIEDMAN
Keyword(s):  
Closed Form ◽  
Transient Response ◽  
Transmission Lines ◽  
Average Error ◽  
Proposed Model ◽  
Newton Raphson ◽  
On Chip ◽  
Interconnect Systems ◽  
Interconnect System ◽  
Raphson Method

With higher operating frequencies, transmission lines are required to model global on-chip interconnects. In this paper, an accurate and efficient solution for the transient response at the far end of a transmission line based on a direct pole extraction of the system is proposed. Closed form expressions of the poles are developed for two special interconnect systems: an RC interconnect and an RLC interconnect with zero driver resistance. By performing a system conversion, the poles of an interconnect system with general circuit parameters are solved. The Newton–Raphson method is used to further improve the accuracy of the poles. Based on these poles, closed form expressions for the step and ramp response are determined. Higher accuracy can be obtained with additional pairs of poles. The computational complexity of the model is proportional to the number of pole pairs. With two pairs of poles, the average error of the 50% delay is 1% as compared with Spectre simulations. With ten pairs of poles, the average error of the 10%-to-90% rise time and the overshoots is 2% and 1.9%, respectively. Frequency dependent effects are also successfully included in the proposed method and excellent match is observed between the proposed model and Spectre simulations.

A new supplier performance evaluation model

Kybernetes ◽  
2010 ◽  
Vol 39 (1) ◽  
pp. 37-54 ◽  
Author(s):  
He‐Yau Kang ◽  
Amy H.I. Lee
Keyword(s):  
Performance Evaluation ◽  
Integrated Circuit ◽  
Evaluation Model ◽  
Pairwise Comparison ◽  
Evaluation Process ◽  
Supplier Evaluation ◽  
Content Type ◽  
Supplier Performance ◽  
Performance Evaluation Model ◽  
Proposed Model

PurposeMost industries have become increasingly competitive nowadays, and a good supply chain relationship is essential for a company to survive and to acquire reasonable profit. Therefore, supplier selection is very important. The purpose of this paper is to propose a novel model for evaluating the performance of suppliers.Design/methodology/approachA supplier performance evaluation model based on analytic hierarchy process (AHP) and data envelopment analysis (DEA) is constructed. DEA is applied first to evaluate quantitative factors, and the results are transformed into pairwise comparison values for AHP analysis. Qualitative factors are also evaluated through AHP analysis, and a final ranking of suppliers can be obtained by combining the quantitative and qualitative results.FindingsThe proposed model can be applied to evaluate and select the most appropriate integrated circuit packaging company for outsourcing. With the incorporation of experts' opinions and the consideration of qualitative and quantitative factors, the model can provide a both subjective and objective supplier performance ranking.Practical implicationsThe proposed model can be tailored and applied to supplier evaluation and selection in other industries.Originality/valueAlthough many models are available for supplier evaluation, this paper considers both the subjective and objective performance characteristics simultaneously in the evaluation process.

scholarly journals Assessment of 50%-Propagation-Delay for Cascaded PCB Non-Linear Interconnect Lines for the High-Rate Signal Integrity Analysis

2013 ◽  
Vol 2 (1) ◽  
pp. 1
Author(s):  
T. Eudes ◽  
B. Ravelo ◽  
R. Al-Hayek
Keyword(s):  
Transfer Function ◽  
Transmission Lines ◽  
Time Domain ◽  
High Speed ◽  
Signal Integrity ◽  
Frequency Dispersion ◽  
Propagation Delay ◽  
High Rate ◽  
Propagation Time ◽  
Time Assessment

This paper presents an enlarged study about the 50-% propagation-time assessment of cascaded transmission lines (TLs). First and foremost, the accurate modeling and measurement technique of signal integrity (SI) for high-rate microelectronic interconnection is recalled. This model is based on the reduced transfer function extracted from the electromagnetic (EM) behavior of the interconnect line RLCG-parameters. So, the transfer function established takes into account both the frequency dispersion effects and the different propagation modes. In addition, the transfer function includes also the load and source impedance effects. Then, the SI analysis is proposed for high-speed digital signals through the developed model. To validate the model understudy, a prototype of microstrip interconnection with w = 500 µm and length d = 33 mm was designed, simulated, fabricated and tested. Then, comparisons between the frequency and time domain results from the model and from measurements are performed. As expected, good agreement between the S-parameters form measurements and the model proposed is obtained from DC to 8 GHz. Furthermore, a de-embedding method enabling to cancel out the connectors and the probe effects are also presented. In addition, an innovative time-domain characterization is proposed in order to validate the concept with a 2.38 Gbit/s-input data signal. Afterwards, the 50-% propagation-time assessment problem is clearly exposed. Consequently an extracting theory of this propagation-time with first order RC-circuits is presented. Finally, to show the relevance of this calculation, propagation-time simulations and an application to signal integrity issues are offered.

Copper-Based Metallization in ULSI Structures: Part II: Is Cu Ahead of Its Time as an On-Chip Interconnect Material?

MRS Bulletin ◽  
1994 ◽  
Vol 19 (8) ◽  
pp. 15-21 ◽  
Author(s):  
Jian Li ◽  
Tom E. Seidel ◽  
Jim W. Mayer
Keyword(s):  
Integrated Circuit ◽  
Process Development ◽  
Random Access ◽  
Random Access Memory ◽  
Dielectric Materials ◽  
Propagation Delay ◽  
Copper Metallization ◽  
Access Memory ◽  
Feature Size ◽  
On Chip

The demand for manufacturing integrated circuit (IC) devices such as dynamic random access memory (DRAM), static random access memory (SRAM), electrically erasable and programmable read only memory (EEPROM) and logic devices with high circuit speed, high packing density and low power dissipation requires the downward scaling of feature sizes in ultralarge-scale integration (ULSI) structures. When chip size becomes smaller, the propagation delay time in a device is reduced. However, the importance of on-chip interconnect RC (resistance capacitance) delay to chip performance, reliability, and processing cost is increasing dramatically. When interconnect feature size decreases and clock frequencies increase, RC time delays become the major limitation in achieving high circuit speeds. The miniaturization of interconnect feature size also severely penalizes the overall performance of the interconnect, such as increasing interconnect resistance and interconnect current densities, which lead to reliability concerns due to electromigration. Lower resistance metal and lower dielectric materials are being considered to replace current Al and SiO2 interconnect materials. Innovative efforts in circuit design, process development, and the implementation of new materials can provide solutions. This issue of the MRS Bulletin focuses on the industrial viewpoint of copper interconnects. (A previous issue of the MRS Bulletin, June 1993, addressed university research approaches to copper metallization.) Articles in this issue, from six major semiconductor companies—IBM, Motorola, AT&T Bell Laboratories, SEMATECH/National Semiconductor, NTT, and Fujitsu—provide a real-world viewpoint of the challenges faced when replacing aluminum with copper. The articles published in both issues also contain a comprehensive list of references (more than 300) to articles, patents, and device applications related to copper metallization for ULSI applications.

Materials Issues and Characterization of Low-k Dielectric Materials

MRS Bulletin ◽  
1997 ◽  
Vol 22 (10) ◽  
pp. 49-54 ◽  
Author(s):  
E. Todd Ryan ◽  
Andrew J. McKerrow ◽  
Jihperng Leu ◽  
Paul S. Ho
Keyword(s):  
Process Integration ◽  
Dielectric Materials ◽  
Propagation Delay ◽  
Thermomechanical Properties ◽  
General Criterion ◽  
Crosstalk Noise ◽  
Total Delay ◽  
Interlayer Dielectrics ◽  
Performance Improvements ◽  
And Performance

Continuing improvement in device density and performance has significantly affected the dimensions and complexity of the wiring structure for on-chip interconnects. These enhancements have led to a reduction in the wiring pitch and an increase in the number of wiring levels to fulfill demands for density and performance improvements. As device dimensions shrink to less than 0.25 μm, the propagation delay, crosstalk noise, and power dissipation due to resistance-capacitance (RC) coupling become significant. Accordingly the interconnect delay now constitutes a major fraction of the total delay limiting the overall chip performance. Equally important is the processing complexity due to an increase in the number of wiring levels. This inevitably drives cost up by lowering the manufacturing yield due to an increase in defects and processing complexity.To address these problems, new materials for use as metal lines and interlayer dielectrics (ILDs) and alternative architectures have surfaced to replace the current Al(Cu)/SiO2 interconnect technology. These alternative architectures will require the introduction of low-dielectric-constant k materials as the interlayer dielectrics and/or low-resistivity conductors such as copper. The electrical and thermomechanical properties of SiO2 are ideal for ILD applications, and a change to material with different properties has important process-integration implications. To facilitate the choice of an alternative ILD, it is necessary to establish general criterion for evaluating thin-film properties of candidate low-k materials, which can be later correlated with process-integration problems.

Low-Dielectric-Constant Materials for ULSI Interlayer-Dielectric Applications

MRS Bulletin ◽  
1997 ◽  
Vol 22 (10) ◽  
pp. 19-27 ◽  
Author(s):  
Wei William Lee ◽  
Paul S. Ho
Keyword(s):  
Packing Density ◽  
Propagation Delay ◽  
Single Chip ◽  
Crosstalk Noise ◽  
Metal Line ◽  
Total Delay ◽  
Interlayer Dielectric ◽  
Low Dielectric ◽  
Interconnect Delay ◽  
Interconnect Technology

Continuing improvement of microprocessor performance historically involves a decrease in the device size. This allows greater device speed, an increase in device packing density, and an increase in the number of functions that can reside on a single chip. However higher packing density requires a much larger increase in the number of interconnects. This has led to an increase in the number of wiring levels and a reduction in the wiring pitch (sum of the metal line width and the spacing between the metal lines) to increase the wiring density. The problem with this approach is that—as device dimensions shrink to less than 0.25 μm (transistor gate length)—propagation delay, crosstalk noise, and power dissipation due to resistance-capacitance (RC) coupling become significant due to increased wiring capacitance, especially interline capacitance between the metal lines on the same metal level. The smaller line dimensions increase the resistivity (R) of the metal lines, and the narrower interline spacing increases the capacitance (C) between the lines. Thus although the speed of the device will increase as the feature size decreases, the interconnect delay becomes the major fraction of the total delay and limits improvement in device performance.To address these problems, new materials for use as metal lines and interlayer dielectrics (ILD) as well as alternative architectures have been proposed to replace the current Al(Cu) and SiO2 interconnect technology.

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