scholarly journals Design SSTL Based Energy Efficient Solar Charge Sensor on FPGA

2019 ◽  
Vol 8 (12) ◽  
pp. 3114-3117
Keyword(s):  
Power Consumption ◽  
Energy Efficient ◽  
Class Ii ◽  
Class I ◽  
Total Power ◽  
Frequency Scaling ◽  
Applied Frequency ◽  
Total Power Consumption ◽  
Fourth Experiment

In this paper we have designed solar charge sensor which is used to make our battery efficient. Component is designed on Virtex 6 FPGA family and applied frequency scaling techniques. During the experiment, we have used different SSTL IO families and calculated total power consumption. In our work we have selected class I and class II from SSTL IO family. For the analysis we have used following range of frequency (20GHz, 40GHz, 60GHz and 80GHz). Firstly, we have worked with SSTL2_I and reduced total power consumption by 51.53%, in second experiment we have worked with SSTL2_I_DCI and reduced consumption of power by 47.18%. In third experiment we choose to work with SSTL2_II and reduced 51.58% in total power consumption. In fourth experiment we opted SSTL15 Io standard and downscale the total power consumption by 51.57%. In fifth we have selected SSTL15_DCI and downscale the power consumption by 49.93%. In sixth experiment we set SSTL18_I_DCI IO standard and consumption minimize by 49.20% in total power. At the end we have mark to be worked with SSTL18_II_DCI which is DCI circuit and found 48.78% reduction in total power consumption.

A Capacitor-Splitting Switching Scheme with Low Total Power Consumption for SAR ADCs

2019 ◽  
Vol 28 (04) ◽  
pp. 1920002 ◽  
Author(s):  
Hao Wang ◽  
Wenming Xie ◽  
Zhixin Chen ◽  
Sijing Cai
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Successive Approximation ◽  
Energy Efficient ◽  
Total Power ◽  
Switching Scheme ◽  
Analog To Digital ◽  
Switching Algorithm ◽  
Good Linearity ◽  
Total Power Consumption

A low-power capacitor-splitting switching algorithm for successive approximation register (SAR) and analog-to-digital converters (ADCs) is proposed. To reduce the total power consumption, it does not require reset energy, which accounts for a large proportion. Besides, energy-efficient one-side double-level switching technique is also utilized from the forth bit cycle. Thus, the proposed switching algorithm requires 26.54 CV[Formula: see text] total switching energy, 16.75% less over the tri-level one. Due to the capacitor-splitting structure, it also shows good linearity performance.

scholarly journals Efficient Operation Method of Aquifer Thermal Energy Storage System Using Demand Response

Energies ◽  
2021 ◽  
Vol 14 (11) ◽  
pp. 3129
Author(s):  
Jewon Oh ◽  
Daisuke Sumiyoshi ◽  
Masatoshi Nishioka ◽  
Hyunbae Kim
Keyword(s):  
Energy Storage ◽  
Power Consumption ◽  
Thermal Energy ◽  
Demand Response ◽  
Thermal Energy Storage ◽  
Heat Storage ◽  
Storage System ◽  
Total Power ◽  
Operation Method ◽  
Total Power Consumption

The mass introduction of renewable energy is essential to reduce carbon dioxide emissions. We examined an operation method that combines the surplus energy of photovoltaic power generation using demand response (DR), which recognizes the balance between power supply and demand, with an aquifer heat storage system. In the case that predicts the occurrence of DR and performs DR storage and heat dissipation operation, the result was an operation that can suppress daytime power consumption without increasing total power consumption. Case 1-2, which performs nighttime heat storage operation for about 6 h, has become an operation that suppresses daytime power consumption by more than 60%. Furthermore, the increase in total power consumption was suppressed by combining DR heat storage operation. The long night heat storage operation did not use up the heat storage amount. Therefore, it is recommended to the heat storage operation at night as much as possible before DR occurs. In the target area of this study, the underground temperature was 19.1 °C, the room temperature during cooling was about 25 °C and groundwater could be used as the heat source. The aquifer thermal energy storage (ATES) system in this study uses three wells, and consists of a well that pumps groundwater, a heat storage well that stores heat and a well that used heat and then returns it. Care must be taken using such an operation method depending on the layer configuration.

scholarly journals A Novel Differential Log-Companding Amplifier for Biosignal Sensing

2016 ◽  
Vol 2016 ◽  
pp. 1-7
Author(s):  
Zigang Dong ◽  
Xiaolin Zhou ◽  
Yuanting Zhang
Keyword(s):  
Power Consumption ◽  
Supply Voltage ◽  
Nonlinear Function ◽  
New Method ◽  
Total Power ◽  
Maximum Output ◽  
Output Current ◽  
Current Range ◽  
Symmetrical Configuration ◽  
Total Power Consumption

We proposed a new method for designing the CMOS differential log-companding amplifier which achieves significant improvements in linearity, common-mode rejection ratio (CMRR), and output range. With the new nonlinear function used in the log-companding technology, this proposed amplifier has a very small total harmonic distortion (THD) and simultaneously a wide output current range. Furthermore, a differential structure with conventionally symmetrical configuration has been adopted in this novel method in order to obtain a high CMRR. Because all transistors in this amplifier operate in the weak inversion, the supply voltage and the total power consumption are significantly reduced. The novel log-companding amplifier was designed using a 0.18 μm CMOS technology. Improvements in THD, output current range, noise, and CMRR are verified using simulation data. The proposed amplifier operates from a 0.8 V supply voltage, shows a 6.3 μA maximum output current range, and has a 6 μW power consumption. The THD is less than 0.03%, the CMRR of this circuit is 74 dB, and the input referred current noise density is166.1 fA/Hz. This new method is suitable for biomedical applications such as electrocardiogram (ECG) signal acquisition.

Exergy Analysis of a Novel Cryogenic Concept for the Liquefaction of Natural Gas Integrated Into an Air Separation Process

2016 ◽  
Author(s):  
S. Tesch ◽  
T. Morosuk ◽  
G. Tsatsaronis
Keyword(s):  
Natural Gas ◽  
Power Consumption ◽  
Exergy Analysis ◽  
Primary Energy ◽  
Separation Process ◽  
Air Separation ◽  
Total Power ◽  
Separation Unit ◽  
Total Power Consumption ◽  
Liquefaction Temperature

The increasing demand for primary energy leads to a growing market of natural gas and the associated market for liquefied natural gas (LNG) increases, too. The liquefaction of natural gas is an energy- and cost-intensive process. After exploration, natural gas, is pretreated and cooled to the liquefaction temperature of around −160°C. In this paper, a novel concept for the integration of the liquefaction of natural gas into an air separation process is introduced. The system is evaluated from the energetic and exergetic points of view. Additionally, an advanced exergy analysis is conducted. The analysis of the concepts shows the effect of important parameters regarding the maximum amount of liquefiable of natural gas and the total power consumption. Comparing the different cases, the amount of LNG production could be increased by two thirds, while the power consumption is doubled. The results of the exergy analysis show, that the introduction of the liquefaction of natural gas has a positive effect on the exergetic efficiency of a convetional air separation unit, which increases from 38% to 49%.

scholarly journals Optimization of Power Consumption for the Design of 802.11n MIMO_OFDM System

2018 ◽  
Vol 26 (4) ◽  
pp. 172-184
Author(s):  
Muthna Jasim Fadhil
Keyword(s):  
Power Consumption ◽  
Orthogonal Frequency Division Multiplexing ◽  
High Speed ◽  
Mimo Systems ◽  
Total Power ◽  
Wireless System ◽  
Generator System ◽  
Total Power Consumption ◽  
Consumption Energy ◽  
High Reduction

In modern systems communication, different methods have been improved to change the prior imitative techniques that process communication data with high speed. It is necessary to improve (OFDM) Orthogonal Frequency Division Multiplexing technique because the development in the guideline communication of wireless system which include security data and transmission data reliability. The applications communications of wireless is important to develop in order to optimize the process of communication leads to reduce the level consumption energy of the output level signal. The architecture of VLSI is used to optimize the performance transceiver in 802.11 n OFDM-MIMO systems, this idea concentrate on the design of 6x6 MIMO_OFDM system in software simulink of MATLAB then using generator system for transfer to code of VHDL and applying in FPGA Xilinx Spartan 3 XC3S200 . The modelsim used to get the simulation while Xilinx power estimator is used to calculate power. The results registered total power consumption about 94mW while compared with previous work  was 136mW which means a high reduction of about 30.8% .

Forecasting Electricity Demand of Shanghai Based on Power Consumption Intensity Decomposition

2011 ◽  
Vol 347-353 ◽  
pp. 2796-2800
Author(s):  
Ying Ling Shi ◽  
Mei Peng
Keyword(s):  
Power Consumption ◽  
Industrial Structure ◽  
Electricity Demand ◽  
Total Power ◽  
Decomposition Model ◽  
Total Power Consumption ◽  
Consumption Intensity

The paper describes the development of economy and electricity in Shanghai, builds a decomposition model of power consumption intensity, and analyzes the impacts of industrial power consumption intensity and industrial structure for the total power consumption intensity of Shanghai. Finally, the paper uses sub-scenarios to forecast electricity demand of Shanghai during Twelfth Five-Year period. The results show that the decrease of total power consumption intensity is mainly due to the decrease of industrial power consumption intensity, and the optimization of industrial structure has some contributions to the decrease of total power consumption as well.

Construction of a Carbon Fiber Reinforced Weft Guide Bar for a Crochet Knitting Machine

2014 ◽  
Vol 136 (6) ◽  
Author(s):  
Mathias Beer ◽  
Yves-Simon Gloy ◽  
Mohit Raina ◽  
Thomas Gries
Keyword(s):  
Carbon Fiber ◽  
Power Consumption ◽  
Total Power ◽  
Fiber Reinforced ◽  
Reduce Power Consumption ◽  
Carbon Fiber Reinforced Plastics ◽  
Reinforced Plastics ◽  
Total Power Consumption ◽  
Fiber Reinforced Plastics ◽  
Carbon Fiber Reinforced

The crochet knitting machine is a warp knitting machine with a weft insertion system placed on a weft guide bar. On standard machines, the weft guide bar is made from aluminum and weighs about 570 g. The single-drive motors, which power the bar, account for 15–20% of the machines total power consumption. The aim of this research was to reduce power consumption by decreasing the mass of the weft guide bar. This was done by constructing the bar from carbon fiber reinforced plastics rather than aluminum, resulting in a mass saving of 260 g.

scholarly journals Novel Low Voltage and Low Power Array Multiplier Design for IoT Applications

Electronics ◽  
2019 ◽  
Vol 8 (12) ◽  
pp. 1429 ◽  
Author(s):  
Jin-Fa Lin ◽  
Cheng-Yu Chan ◽  
Shao-Wei Yu
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Low Voltage ◽  
Full Adder ◽  
Total Power ◽  
Iot Applications ◽  
Delay Cell ◽  
Total Power Consumption ◽  
Array Multiplier ◽  
Cell Circuit

In this paper, a novel latch-adder based multiplier design, targeting low voltage and low power IoT applications is presented. It employs a semi-dynamic (dynamic circuit with static keeper circuit) full adder design which efficiently incorporates the level sensitive latch circuit with the adder cell. Latch circuit control signals are generated by a chain of delay cell circuits. They are applied to each row of the adder array. This row-wise alignment ensures an orderly procedure, while successfully removing spurious switching resulting in reduced power consumption. Due to the delay cell circuit of our design is also realized by using full adder. Therefore, it is unnecessary to adjust the transistor sizes of the delay cell circuit deliberately. Post-layout simulation results on 8 × 8 multiplier design show that the proposed design has the lowest power consumption of all design candidates. The total power consumption saving compared to conventional array multiplier designs is up to 38.6%. The test chip measurement shows successful operations of our design down to 0.41 V with a power consumption of only 427 nW with a maximum frequency 500 KHz.

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