scholarly journals A Ring Oscillator Based Random Generator for Cryptography Applications

A ring oscillator based Random number generator (RNG) for Cryptography applications is presented. The paper explains about the requirements and generation of high randomness based codes, used to improve the security in data communication. The methodology used is sampling technique, adopted in the oscillator for the random number generation. To get better randomness in the output bits of RNG, a processor module based on Linear feedback shift register is used. The proposed RNG is designed with bit rate is 100kb/s, with a power consumption of 37µw. After implementation in hardware, this can be used for cryptography encryption applications to enhance the security. The system is simulated and synthesized with Xilinx ISE and the results are compared with the existing system based on randomness, power consumption, etc.

Author(s):  
Padmapriya Praveenkumar ◽  
Santhiya Devi R. ◽  
Amirtharajan Rengarajan ◽  
John Bosco Balaguru Rayappan

Nano industries have been successful trendsetters for the past 30 years, in escalating the speed and dropping the power necessities of nanoelectronic devices. According to Moore's law and the assessment created by the international technology roadmap for semiconductors, beyond 2020, there will be considerable restrictions in manufacturing IC's based on CMOS technologies. As a result, the next prototype to get over these effects is quantum-dot cellular automata (QCA). In this chapter, an efficient quantum cellular automata (QCA) based random number generator (RNG) is proposed. QCA is an innovative technology in the nano regime which guarantees large device density, less power dissipation, and minimal size as compared to the various CMOS technologies. With the aim to maximise the randomness in the proposed nano communication, a linear feedback shift register (LFSR) keyed multiplexer with ring oscillators is developed. The developed RNG is simulated using a quantum cellular automata (QCA) simulator tool.


Nowadays security has become a great concern in the field of computer science and information technology. In order to protect data from unintended users and to achieve a desirable level of security, several cryptographic algorithms based on various technology have been proposed. Linear Feedback Shift Register (LFSR) may play an important role in the design of such cryptographic algorithms. LFSR based cryptographic algorithms are often lightweight in nature and are more suitable for resource constraining devices. In this paper we present a detailed analysis of LFSR and design of LFSR to implement cryptographic algorithms.


Electronics ◽  
2020 ◽  
Vol 9 (1) ◽  
pp. 195
Author(s):  
Hwasoo Shin ◽  
Soyeon Choi ◽  
Jiwoon Park ◽  
Byeong Yong Kong ◽  
Hoyoung Yoo

This paper presents a novel error detection linear feedback shift register (ED-LFSR), which can be used to realize error detection with a small hardware overhead for various applications such as error-correction codes, encryption algorithms and pseudo-random number generation. Although the traditional redundancy methods allow the incorporation of the error detection/correction capability in the original LFSRs, they suffer from a considerable amount of hardware overheads. The proposed ED-LFSR alleviates such problems by employing the parity check technique. The experimental results indicate that the proposed ED-LFSR requires an additional area of only 31.1% compared to that required by the conventional LFSR and it saves 39.1% and 31.9% of the resources compared to the corresponding utilization of the hardware and time redundancy methods.


Author(s):  
HARSH KUMAR VERMA ◽  
RAVINDRA KUMAR SINGH

Linear Feedback Shift Register based Unique Random Number Generator is an enhancement of Random Number generator with the additional property that any number generated by a unique random number generator can’t be duplicated. As per users demand for not duplicated random numbers in some applications like transferring a random number over the network on the behalf of actual character of the message for security point of view, existence of unique random number generators are very essential. In this paper LFSR [1] (Linear Feedback Shift Register) is used to implement the proposed concept of unique random number generator. Using LFSR is a faster approach for generating random sequences because it requires only X-OR operations and shift registers that’s why its implementation is very easy in software as well as in hardware [2, 3]. We can easily modify the LFSR and produce different random sequences. So it is the best option for using LFSR in unique random number generator.


2021 ◽  
Vol 11 (8) ◽  
pp. 3330
Author(s):  
Pietro Nannipieri ◽  
Stefano Di Matteo ◽  
Luca Baldanzi ◽  
Luca Crocetti ◽  
Jacopo Belli ◽  
...  

Random numbers are widely employed in cryptography and security applications. If the generation process is weak, the whole chain of security can be compromised: these weaknesses could be exploited by an attacker to retrieve the information, breaking even the most robust implementation of a cipher. Due to their intrinsic close relationship with analogue parameters of the circuit, True Random Number Generators are usually tailored on specific silicon technology and are not easily scalable on programmable hardware, without affecting their entropy. On the other hand, programmable hardware and programmable System on Chip are gaining large adoption rate, also in security critical application, where high quality random number generation is mandatory. The work presented herein describes the design and the validation of a digital True Random Number Generator for cryptographically secure applications on Field Programmable Gate Array. After a preliminary study of literature and standards specifying requirements for random number generation, the design flow is illustrated, from specifications definition to the synthesis phase. Several solutions have been studied to assess their performances on a Field Programmable Gate Array device, with the aim to select the highest performance architecture. The proposed designs have been tested and validated, employing official test suites released by NIST standardization body, assessing the independence from the place and route and the randomness degree of the generated output. An architecture derived from the Fibonacci-Galois Ring Oscillator has been selected and synthesized on Intel Stratix IV, supporting throughput up to 400 Mbps. The achieved entropy in the best configuration is greater than 0.995.


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