scholarly journals RTL Design of Efficient High-Speed Adders using Quantum-Dot Cellular Automatation

2019 ◽  
Vol 8 (2S11) ◽  
pp. 2853-2857

This article presents the design of high-speed adders using Quantum cellular automata. Quantum Automata is an efficient evaluation platform than CMOS in nanotechnology. Power, surface and performance play a virtual role in nanotechnology. Quantum Automata is an emerging technology in nanotechnology. QCA provides more speed, less power consumption and large scale integration in VLSI. By using Quantum-Dot cellular automata, we can reduce the power of leaks. Generally, for transferring the data and store data, electric fields are used in CMOS technology but in QCA, storing the data and transfer the data done by electronic polarization. This article presents different combinational logic circuits depend on QCA technology. The proposed modified CSLA (carry select adder) offer the best results of delay compared to the Ripple carry adder (RCA).

Author(s):  
Esam AlKaldy ◽  
Ali H Majeed ◽  
Mohd Shamian Zainal ◽  
Danial MD Nor

<p>Quantum-dot Cellular Automata (QCA) is one of the most important computing technologies for the future and will be the alternative candidate for current CMOS technology. QCA is attracting a lot of researchers due to many features such as high speed, small size, and low power consumption. QCA has two main building blocks (majority gate and inverter) used for design any Boolean function. QCA also has an inherent capability that used to design many important gates such as XOR and Multiplexer in optimal form without following any Boolean function. This paper presents a novel design 2:1 QCA-Multiplexer in two forms. The proposed design is very simple, highly efficient and can be used to produce many logical functions. The proposed design output comes from the inherent capabilities of quantum technology. New 4:1 QCA-Multiplexer has been built using the proposed structure. The output waveforms showed the wonderful performance of the proposed design in terms of the number of cells, area, and latency.</p>


Author(s):  
Vardhana M. ◽  
Anil Kumar Bhat

Background: Security is one of the fundamental and essential factors, which has to be addressed in the field of communication. Communication refers to the exchange of useful information between two or more nodes. Sometimes it is required to exchange some of the confidential information such as a company’s logo, which needs to be hidden from the third person. The data that is being exchanged between these nodes has to be kept confidential and secured from unintended users. The three fundamental components of security are confidentiality, integrity and authentication. The data that is being exchanged has to be confidential, and only the authorized party should have access to the information that is being exchanged. One of the key methods for securing the data is encryption. Objective: The main objective of this paper was to address the problem of data hiding and security in communication systems. There is a need for having hardware resources for having high speed data security and protection. Methods: In this paper, we implemented image watermarking using LSB technique to hide a secret image, and employed encryption using Advanced Encryption Standard, to enhance the security of the image. An image is a two dimensional signal, with each pixel value representing the intensity level. The secure transmission of the image along the channel is a challenging task, because of the reason that, any individual can access it, if no security measures are taken. Conclusion: An efficient method of digital watermarking has been implemented with increased security and performance parameters are presented. Results: In this paper, hardware realization of image watermarking/encryption and dewatermarking/ decryption is implemented using Very Large Scale Integration. The design is verified by means of co-simulation using MATLAB and Xilinx. The paper also presents the performance parameters of the design, with respect to speed, area and power.


Electronics ◽  
2020 ◽  
Vol 9 (6) ◽  
pp. 1036
Author(s):  
Nuriddin Safoev ◽  
Jun-Cheol Jeon

A multiplier is one of the main units for digital signal processing and communication systems. In this paper, a high speed and low complexity multiplier is designed on the basis of quantum-dot cellular automata (QCA), which is considered promising nanotechnology. We focus on Vedic multiplier architectures according to Vedic mathematics from ancient Indian sculptures. In fact, an adder is an important block in the design of almost all types of multipliers and a ripple carry adder is used to design simple multiplier implementations. However, a high-speed multi-bit multiplier requires high-speed adder owing to carry propagation. Cell-interaction-based QCA adders have better improvements over conventional majority-gate-based adders. Therefore, a two-bit Vedic multiplier is proposed in QCA and it is used to implement a four-bit form of the multiplier. The proposed architecture has a lower cell count and area compared to other existing structures. Moreover, simulation results demonstrate that the proposed design is sustainable and can be used to realize complex circuit designs for QCA communication networks.


2021 ◽  
Author(s):  
Saeid Seyedi ◽  
Behrouz Pourghebleh

Abstract Since the scaling of transistors is growing rapidly, the need for an efficient alternative for the Complementary Metal-Oxide-Semiconductor (CMOS) technology to obtain further and extra processes in the circuits has known as the main problem. Over the last decade, Quantum-dot Cellular Automata (QCA) technology due to its excellent potential in developing designs with low-power consumption, high-speed, and high-density has been recognized as a suitable replacement to CMOS technology. In this regard, lowering the number of gates, the amount of cell count, and delay has been emphasized in the design of QCA-based circuits. Adders as the main unit in logic circuits and digital arithmetic play an important role in constructing various effective QCA designs. In this regard, Ripple Carry Adder (RCA) is a simple form of adders and due to its remarkable features can be useful to reach circuits with the minimum required area and power consumption. Therefore, in this study, a new design for RCA in QCA technology is recommended to reduce the cell count, amend the complexity, and decrease the latency. To verify the correctness of the suggested circuit, the QCADesigner version 2.0.3 as a well known simulator has been used. The evaluation results confirm that the proposed design has approximately 28.6% improvement in cell count in comparison to the state-of-the-art four-bit coplanar RCA designs in QCA technology. Also, the obtained results designate the effectiveness of the advised plan.


2021 ◽  
Vol 11 (18) ◽  
pp. 8717
Author(s):  
Mohsen Vahabi ◽  
Pavel Lyakhov ◽  
Ali Newaz Bahar

One of the emerging technologies at the nanoscale level is the Quantum-Dot Cellular Automata (QCA) technology, which is a potential alternative to conventional CMOS technology due to its high speed, low power consumption, low latency, and possible implementation at the atomic and molecular levels. Adders are one of the most basic digital computing circuits and one of the main building blocks of VLSI systems, such as various microprocessors and processors. Many research studies have been focusing on computable digital computing circuits. The design of a Full Adder/Subtractor (FA/S), a composite and computing circuit, performing both the addition and the subtraction processes, is of particular importance. This paper implements three new Full Adder/Subtractor circuits with the lowest number of cells, lowest area, lowest latency, and a coplanar (single-layer) circuit design, as was shown by comparing the results obtained with those of the best previous works on this topic.


2020 ◽  
Vol 10 (4) ◽  
pp. 534-547
Author(s):  
Chiradeep Mukherjee ◽  
Saradindu Panda ◽  
Asish K. Mukhopadhyay ◽  
Bansibadan Maji

Background: The advancement of VLSI in the application of emerging nanotechnology explores quantum-dot cellular automata (QCA) which has got wide acceptance owing to its ultra-high operating speed, extremely low power dissipation with a considerable reduction in feature size. The QCA architectures are emerging as a potential alternative to the conventional complementary metal oxide semiconductor (CMOS) technology. Experimental: Since the register unit has a crucial role in digital data transfer between the electronic devices, such study leading to the design of cost-efficient and highly reliable QCA register is expected to be a prudent area of research. A thorough survey on the existing literature shows that the generic models of Serial-in Serial Out (SISO), Serial-in-Parallel-Out (SIPO), Parallel-In- Serial-Out (PISO) and Parallel-in-Parallel-Out (PIPO) registers are inadequate in terms of design parameters like effective area, delay, O-Cost, Costα, etc. Results: This work introduces a layered T gate for the design of the D flip flop (LTD unit), which can be broadly used in SISO, SIPO, PISO, and PIPO register designs. For detection and reporting of high susceptible errors and defects at the nanoscale, the reliability and defect tolerant analysis of LTD unit are also carried out in this work. The QCA design metrics for the general register layouts using LTD unit is modeled. Conclusion: Moreover, the cost metrics for the proposed LTD layouts are thoroughly studied to check the functional complexity, fabrication difficulty and irreversible power dissipation of QCA register layouts.


Author(s):  
A. Arunkumar Gudivada ◽  
K. Jayaram Kumar ◽  
Srinivasa Rao Jajula ◽  
Durga Prasad Siddani ◽  
Praveen Kumar Poola ◽  
...  

2011 ◽  
Author(s):  
Βασίλειος Μαρδύρης

In last decades exponential reduction of integrated circuits feature size and increase in operating frequency was achieved in VLSI fabrication industry using the conventional CMOS technology. However the CMOS technology faces serious challenges as the CMOS transistor reaches its physical limits, such as ultra thin gate oxides, short channel effects, doping fluctuations and increased difficulty and consequently increased lithography cost in the nanometer scale. It is projected that the CMOS technology, in its present state will reach its limits when the transistors channel length reaches approximatly 7 nm, probably near 2019. Emerging technologies have been a topic of great interest in the last few years. The emerging technologies in nanoelectronics provide new computing possibilities that arise from their extremely reduced feature sizes. Quantum Cellular Automata (QCA) is one of the most promising emerging technologies in the fast growing area of nanoelectronics. QCA relies mostly on Coulombic interactions and uses innovative processing techniques which are very different from the CMOS-based model. QCAs are not only a new nanoelectronic model but also provide a new method of computation and information process. In QCA circuits computation and data transfer occurs simultaneously. Appling the QCA technology, the elementary building component (QCA cells) cover an area of a few nanometers. For this feature sizes the integration can reach values of 1012 cells/cm2 and the circuit switching frequency the THz level. The implementation of digital logic using QCA nanoelectronic circuits not only drives the already developed systems based on conventional technology to the nanoelectronic era but improves their performance significantly. At the present Ph.D. thesis, a study of QCA circuit clocking schemes is presented showing how these schemes contribute to the robustness of QCA circuits. A novel design of a QCA 2 to 1 multiplexer is presented. The QCA circuit is simulated and its operation is analyzed. A modular design and simulation methodology is developed for the first time. This methodology can be used to design 2n to 1 QCA multiplexers using the 2 to 1 QCA multiplexer as a building block. The design methodology is formulated in order to increase the circuit stability.Furthermore in this Ph.D. thesis, a novel design of a small size, modular quantum-dot cellular automata (QCA) 2n to 1 multiplexer is proposed, These multiplexers can be used for memory addressing. The design objective is to develop an evolving modular design methodology which can produce QCA 2n to 1 multiplexer circuits, improved in terms of circuit area and operating frequency. In these implementations the circuit stability was a major issue and was considered carefully. In the recent years, Cellular Automata (CAs) have been widely used in order to model and simulate physical systems and also to solve scientific problems. CAs have also been successfully used as a VLSI architecture and proved to be very efficient in terms of silicon-area utilization and clock-speed maximization. In the present Ph.D. thesis a design methodology is developed for the first time, which can be used to design CA models using QCA circuitry. The implementation of CAs using QCA nanoelectronic circuits significantly improves their performance due to the unique properties of the nanoelectronic circuits. In this Ph.D. thesis a new CAD system we develope for the first time, and was named Design Automation Tool of 1-D Cellular Automata using Quantum Cellular Automata (DATICAQ), that builds a bridge between one-dimensional CAs as models of physical systems and processes and one-dimensional CAs as a nanoelectronic architecture. The CAD system inputs are the CA dimensionality, size, local rule, and the initial and boundary conditions imposed by the particular problem. DATICAQ produces as output the layout of the QCA implementation of the particular one-dimensional CA model. The proposed system also provides the simulation input vectors and their corresponding outputs, in order to simplify the simulation process. No prior knowledge of QCA circuit designing is required by the user. DATICAQ has been tested for a large number of QCA circuits. Paradigms of QCA circuits implementing CA models for zero and periodic boundary conditions are presented in the thesis. Simulations of CA models and the corresponding QCA circuits showed that the CA rules and models have been successfully implemented. At the present Ph.D. thesis, the design of large scale QCA circuits is analyzed and a study of the problems arising on complex algorithm implementation using QCAs is presented. One of the most important problems of the large scale QCA circuits is the synchronization of the internal signals of the circuit between the subsystems of the large QCA circuit. This problem becomes more difficult when the circuit includes signal loops. In the present thesis a methodology and a QCA circuit is presented for the first time, which solves the above mentioned synchronization problem. The QCA circuit implements the Firing Squad Synchronization Algorithm proposed by Mazoyer in order to solve the synchronization problem. The implementation was obtained using a one-dimensional 3-bit digital CA model. The QCA circuit is simulated and its operation is analyzed.


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