PERAMALAN INFLASI DI INDONESIA MENGGUNAKAN METODE AUTOREGRESSIVE MOVING AVERAGE (ARMA)

A good inflation rate for a country is an inflation rate that has a low and stable value so that able to realize fast and controlled economic growth. Forecasting can be one of the steps that can provide an overview of the value of inflation in Indonesia for the government or related agencies to formulate and maintain inflation stability in Indonesia. In this study, a forecasting analysis was carried out to determine the prediction of inflation in Indonesia in 2021 using the Autoregressive Moving Average (ARMA) method. From the results of the research that has been done, the best model to predict this case is using the ARMA model (3,0,0) because it produces the smallest AIC value of 0.2373 and the smallest RMSE of 7.81. From this model, the results of forecasting inflation rates for the months of May to December 2021 are also obtained with a range of 0.1% to 0.3%. The graphic pattern of the predicted results follows the actual data line pattern, which means that this model is good to use. Abstrak Tingkat inflasi yang baik bagi suatu negara adalah tingkat inflasi yang memiliki nilai yang rendah dan stabil, sehinga mampu mewujudkan pertumbuhan ekonomi yang cepat dan terkendali. Peramalan dapat menjadi salah satu langkah yang dapat memberikan gambaran nilai inflasi di Indonesia bagi pemerintah atau badan yang terkait untuk menyusun dan mempertahankan kestabilan inflasi di Indonesia. Dalam penelitian ini, dilakukan analisis peramalan untuk mengetahui prediksi angka inflasi di Indonesia tahun 2021 menggunakan metode Autoregresif Moving Average (ARMA). Dari hasil penelitian yang telah dilakukan, model terbaik untuk meramalkan kasus ini yaitu menggunakan model ARMA (3,0,0) karena menghasilkan nilai AIC paling kecil yaitu 0.2373 dan RMSE terkecil sebesar 7.81. Dari model tersebut juga didapatkan hasil peramalan angka inflasi untuk bulan Mei hingga Desember 2021 dengan kisaran 0.1% hingga 0.3%. Pola grafik dari hasil prediksi mengikuti pola garis data aktual yang berarti bahwa model ini baik untuk digunakan.

Comparative Analysis in Terms of Power and Delay of the Different Sense Amplifier Topologies

To read the data from the memory in each of the devices is crucial. In the modern-day VLSI, world need high-speed devices to satisfy the demand for application such as the Internet of Things (IoT) and System on Chip (Soc). We have implemented the different types of existing sense amplifiers to investigate the working and application point of view. Every sense amplifier has its own advantage. Each of the sense amplifiers is focusing basically on the charging and discharging of Bit Line (BL), Bit Line Bar (BLB) in case of Voltage sense and Data Line (DL), Data Line Bar (DLB) in case of current sense. The waveform of the Voltage sense and current sense clearly shown. Performance comparison based on Sensing Delay, Power, and Supply variation at UMC 65nm CMOS technology node using CADENCE Virtuoso tool.

Design and mathematical analysis of a 7T SRAM cell with enhanced read SNM using PMOS as an access transistor

Purpose This work is proposed for low power energy-efficient applications like laptops, mobile phones, and palmtops. In this study, P-channel metal–oxide–semiconductor (PMOS)’s are used as access transistor in 7 transistors (7 T) Static Random Access Memory (SRAM) cell, and the theoretical Static Noise Margin (SNM) analysis for the proposed cell is also performed. A cell is designed using 7 T which consists of 4 PMOS and 3 NMOS. In this paper write and hold SNM is addressed and read SNM is also calculated for the proposed 7 T SRAM cell. Design/methodology/approach The authors have replaced N-channel metal–oxide–semiconductor (NMOS) access transistors with the PMOS access transistors, which results in proper data line recovery and provides the desired coupling. An error is likely to occur, if the read operation is performed too often probably by using the NMOS pass gate. It results in an improper recovery of the data line. Instead, by using PMOS as a pass gate, the time required for read operation can be brought down. As we know the mobility (µ) of the PMOS transistor is low, so the authors have used this property into the proposed design. When a low signal is applied to its control gate, the PMOS transistor come up with the desired coupling, when working as a pass gate. Findings Feedback switched transistor is used in the proposed circuit, which plays an important role in the write operation. This transistor is in OFF state and PMOS’s work as access transistor, when the proposed cell operating in read mode. This helps in the reduction of power. This work is simulated using UMC 40 nm technology node in the cadence virtuoso environment. The simulated result shows that, write power saving of 51.54% and 61.17%, hold power saving of 25.68% and 48.93% when compared with reported 7 T and 6 T, respectively. Originality/value The proposed 7 T SRAM cell provides proper data line recovery at a lower voltage when PMOS works as the access transistor. Power consumption is very less in this technique and it is best suitable for low power applications.

A Novel Low-Power Synchronous Preamble Data Line Chip Design for Oscillator Control Interface

In this paper, a novel low-power synchronous preamble data line protocol chip design for serial communication is proposed. The serial communication only uses two wires, chip select (CS) and secure digital (SD), to transmit and receive data between two devices. The proposed protocol aims to use a fewer number of wires for the interface, therefore reducing the complexity as well as the area of the chip design. Moreover, it increases the efficiency through a synchronous serial communication-controlled oscillator. The low-power synchronous preamble data line protocol design was successfully verified using a field-programmable gate array (FPGA) as a master device and a real chip as a slave device. The signals are checked through the use of a logic analyzer. The realized low-power synchronous preamble data line protocol chip design has a gate count of only 5.07 K gates, a low power dissipation of 12 mW, and a chip area of 453,260 μm2 using the Taiwan semiconductor manufacturing company (TSMC) 0.18 μm CMOS process. Compared with the three-wire serial peripheral interface (SPI) protocol, the proposed design has the advantages of having a lower cost and a lower power consumption.

Squamanitaceae and Three New Species of Squamanita Parasitic on Amanita Basidiomes

The systematic position of the enigmatic genus Squamanita (Agaricales, Basidiomycota) is largely unknown. Together with Cystoderma and Phaeolepiota, they were categorized as belonging in the tribe Cystodermateae. In this study, with newly generated sequences of the type species of the genus Squamanita, namely S. schreieri, and sequences of a few species of Cystodermateae, the phylogeny of this “tribe” is reinvestigated with a concatenated (28S-5.8S-18S) dataset. Our study reveals that Squamanita and Phaeolepiota-Cystoderma are indeed sister groups with moderate statistic support (MLBS/PP = 80/1), and Squamanita is a monophyletic clade with highly statistic support (MLBS/PP = 92/1). The family name Squamanitaceae is resurrected and emended to accommodate the three genera. Meanwhile, another concatenated (ITS-28S-18S) dataset is used to investigate the phylogenetic relationship and species delimitation in Squamanita. Our data indicated that “S. umbonata” from North America, Europe, East Asia, and Central America harbors a complex of species, and species of Squamanita can parasitize species of Amanita, besides other fungal species. Squamanita mira parasitizes A. kitamagotake (A. sect. Caesareae), while S. orientalis and S. sororcula are parasites of species belonging to the A. sepiacea complex (A. sect. Validae). “Squamanita umbonata” from Italy occurs on A. excelsa (A. sect. Validae). Three new species of Squamanita from East Asia, viz. S. mira, S. orientalis and S. sororcula are documented with morphological, multi-genes phylogenetic, ecological data, line drawings, and photographs and compared with similar species.

Optimal grid resolution for precipitation maps from commercial microwave link networks

High-resolution precipitation observation based on signal attenuation in a Commercial Microwave Link (CML) network is an emerging technique that is becoming more and more used. Commonly, the raw data – line measurements from successive time steps – are mapped onto a grid to estimate precipitation fields with a full spatio-temporal coverage. Assuming the CML-estimated precipitation to be accurate, the attainable resolutions in time and space are primarily dependent on two factors: (i) the spatial distribution of the link network and (ii) the spatial correlation properties of the precipitation. Here we outline a pragmatic method for estimating the optimal resolution based on variogram analysis. The method is demonstrated using a CML network and a representative variogram in Stockholm, Sweden. Conceivable applications include preliminary investigations in cities considering starting CML-based precipitation observations.