scholarly journals Low Complexity Non Maximally Coefficient Symmetry Multi Rate Filter Bank for Wideband Channelization

2021 ◽  
Vol 20 ◽  
pp. 57-65
Author(s):  
Kirti Samir Vaidya ◽  
C. G. Dethe ◽  
S. G. Akojwar
Keyword(s):  
Wireless Communication ◽  
Power Consumption ◽  
Input Signal ◽  
Filter Bank ◽  
Software Radio ◽  
Low Complexity ◽  
Polyphase Filter ◽  
The Individual ◽  
Hardware Efficiency ◽  
Communication Standard

For extracting the individual channels from input signal of wideband, Software Radio Channelizer was often used on multi-standard wireless communication. Despite the effective channelizer design that decreases the complexity of computational, delay and power consumption is challenging. Thus, to promote the effectiveness of the channelizer, we have provided the Non-Maximally Coefficient Symmetry Multirate Filter Bank. For this, a sharp wideband channelizer is designed to be using the latest class of masking responses with Non-maximally Decimated Polyphase Filter. Moreover, coefficient symmetry is incorporated into the Non-Maximally Coefficient Symmetry Multirate Filter Bank to improve the hardware efficiency and functionality of the proposed schemes. To prove the complexity enhancement of the proposed system, the design is analyzed with communication standard with existing methods.

scholarly journals Low Complexity Non Maximally Coefficient Symmetry Multi Rate Filter Bank for Wideband Channelization

2021 ◽  
Author(s):  
Kirti Samir Vaidya ◽  
Dethe C.G ◽  
S. G. Akojwar
Keyword(s):  
Wireless Communication ◽  
Power Consumption ◽  
Input Signal ◽  
Filter Bank ◽  
Software Radio ◽  
Low Complexity ◽  
Polyphase Filter ◽  
The Individual ◽  
Hardware Efficiency ◽  
Communication Standard

Abstract For extracting the individual channels from input signal of wideband, Software Radio Channelizer was often used on multi-standard wireless communication. Despite the effective channelizer design that decreases the complexity of computational, delay and power consumption is challenging. Thus, to promote the effectiveness of the channelizer, we have provided the Non-Maximally Coefficient Symmetry Multirate Filter Bank. For this, a sharp wideband channelizer is designed to be using the latest class of masking responses with Non-maximally Decimated Polyphase Filter. Moreover, coefficient symmetry is incorporated into the Non-Maximally Coefficient Symmetry Multirate Filter Bank to improve the hardware efficiency and functionality of the proposed schemes. To prove the complexity enhancement of the proposed system, the design is analyzed with communication standard with existing methods.

scholarly journals Design of a Power-Efficient Low Complexity Non Maximally Coefficient Symmetry Multi Rate Filter Bank for Wideband Channelization

2021 ◽  
Vol 15 ◽  
pp. 883-894
Author(s):  
Kirti Samir Vaidya ◽  
C. G. Dethe ◽  
S. G. Akojwar
Keyword(s):  
Wireless Communication ◽  
Software Defined Radio ◽  
Filter Bank ◽  
Radio Channel ◽  
Software Radio ◽  
Low Complexity ◽  
Power Efficient ◽  
Complex Part ◽  
Computing Complexity ◽  
Hardware Efficiency

A solution for existing and upcoming wireless communication standards is a software-defined radio (SDR) that extracts the desired radio channel. Channelizer is supposed to be the computationally complex part of SDR. In multi-standard wireless communication, the Software Radio Channelizer is often used to extract individual channels from a wideband input signal. Despite the effective channelizer design that reduces computing complexity, delay and power consumption remain a problem. Thus, to promote the effectiveness of the channelizer, we have provided the Non-Maximally Coefficient Symmetry Multirate Filter Bank. In this paper, to improve the hardware efficiency and functionality of the proposed schemes, we propose a polyphase decomposition and coefficient symmetry incorporated into the Non-Maximally Coefficient Symmetry Multirate Filter Bank. For sharp wideband channelizers, the proposed methods are suitable. Furthermore, polyphase decomposition filter and coefficient symmetry is incorporated into the Non-Maximally Coefficient Symmetry Multirate Filter Bank to improve the hardware efficiency, power efficient, flexibility, reduce hardware size and functionality of the proposed methods. To prove the complexity enhancement of the proposed system, the design to be the communication standard for complexity comparison.

scholarly journals Improving Generalized Discrete Fourier Transform (GDFT) Filter Banks with Low-Complexity and Reconfigurable Hybrid Algorithm

Digital ◽  
2020 ◽  
Vol 1 (1) ◽  
pp. 1-17
Author(s):  
Temidayo Otunniyi ◽  
Hermanus Myburgh
Keyword(s):  
Fourier Transform ◽  
Integrated Circuits ◽  
Power Consumption ◽  
Discrete Fourier Transform ◽  
High Speed ◽  
Filter Bank ◽  
Filter Design ◽  
Low Complexity ◽  
Lookup Table ◽  
Research Attention

With ever-increasing wireless network demands, low-complexity reconfigurable filter design is expected to continue to require research attention. Extracting and reconfiguring channels of choice from multi-standard receivers using a generalized discrete Fourier transform filter bank (GDFT-FB) is computationally intensive. In this work, a lower compexity algorithm is written for this transform. The design employs two different approaches: hybridization of the generalized discrete Fourier transform filter bank with frequency response masking and coefficient decimation method 1; and the improvement and implementation of the hybrid generalized discrete Fourier transform using a parallel distributed arithmetic-based residual number system (PDA-RNS) filter. The design is evaluated using MATLAB 2020a. Synthesis of area, resource utilization, delay, and power consumption was done on a Quartus 11 Altera 90 using the very high-speed integrated circuits (VHSIC) hardware description language. During MATLAB simulations, the proposed HGDFT algorithm attained a 66% reduction, in terms of number of multipliers, compared with existing algorithms. From co-simulation on the Quartus 11 Altera 90, optimization of the filter with PDA-RNS resulted in a 77% reduction in the number of occupied lookup table (LUT) slices, an 83% reduction in power consumption, and an 11% reduction in execution time, when compared with existing methods.

Design and Implementation of an Efficient Parallel LFSR Architecture for Wireless Communication Systems

2019 ◽  
Vol 14 ◽  
Author(s):  
A. Suresh Babu ◽  
B. Anand
Keyword(s):  
Wireless Communication ◽  
Power Consumption ◽  
Low Power ◽  
Communication Systems ◽  
High Speed ◽  
Design Tool ◽  
Shift Register ◽  
Linear Feedback ◽  
Wireless Communication Systems ◽  
Coverage Area

: A Linear Feedback Shift Register (LFSR) considers a linear function typically an XOR operation of the previous state as an input to the current state. This paper describes in detail the recent Wireless Communication Systems (WCS) and techniques related to LFSR. Cryptographic methods and reconfigurable computing are two different applications used in the proposed shift register with improved speed and decreased power consumption. Comparing with the existing individual applications, the proposed shift register obtained >15 to <=45% of decreased power consumption with 30% of reduced coverage area. Hence this proposed low power high speed LFSR design suits for various low power high speed applications, for example wireless communication. The entire design architecture is simulated and verified in VHDL language. To synthesis a standard cell library of 0.7um CMOS is used. A custom design tool has been developed for measuring the power. From the results, it is obtained that the cryptographic efficiency is improved regarding time and complexity comparing with the existing algorithms. Hence, the proposed LFSR architecture can be used for any wireless applications due to parallel processing, multiple access and cryptographic methods.

scholarly journals Low-Complexity High-Throughput QC-LDPC Decoder for 5G New Radio Wireless Communication

Electronics ◽  
2021 ◽  
Vol 10 (4) ◽  
pp. 516
Author(s):  
Tram Thi Bao Nguyen ◽  
Tuy Nguyen Tan ◽  
Hanho Lee
Keyword(s):  
Wireless Communication ◽  
High Throughput ◽  
Low Complexity ◽  
Ldpc Decoder ◽  
Processor Architectures ◽  
New Radio ◽  
Decoder Architecture ◽  
Check Node ◽  
Information Update ◽  
Wireless Standards

This paper presents a pipelined layered quasi-cyclic low-density parity-check (QC-LDPC) decoder architecture targeting low-complexity, high-throughput, and efficient use of hardware resources compliant with the specifications of 5G new radio (NR) wireless communication standard. First, a combined min-sum (CMS) decoding algorithm, which is a combination of the offset min-sum and the original min-sum algorithm, is proposed. Then, a low-complexity and high-throughput pipelined layered QC-LDPC decoder architecture for enhanced mobile broadband specifications in 5G NR wireless standards based on CMS algorithm with pipeline layered scheduling is presented. Enhanced versions of check node-based processor architectures are proposed to improve the complexity of the LDPC decoders. An efficient minimum-finder for the check node unit architecture that reduces the hardware required for the computation of the first two minima is introduced. Moreover, a low complexity a posteriori information update unit architecture, which only requires one adder array for their operations, is presented. The proposed architecture shows significant improvements in terms of area and throughput compared to other QC-LDPC decoder architectures available in the literature.

Sign in / Sign up

Export Citation Format

Share Document