The Design of Fire Proof Leakage Current Circuit Protective Device Based on AVR MCU

2012 ◽  
Vol 241-244 ◽  
pp. 172-175
Author(s):  
An Song Feng ◽  
Qing Hui Wang ◽  
Xiao Yu Ge
Keyword(s):  
Leakage Current ◽  
Power Supply ◽  
Protective Device ◽  
Device Design ◽  
Software And Hardware ◽  
Avr Mcu

Fire proof leakage current circuit protective device is a kind of protect devices. It monitors the leakage current of power supply. When they have some trouble, it shuts down power supply. Beginning from the design, the paper introduces the process of Fire proof leakage current circuit protective device design including software and hardware based on AVR MCU.

scholarly journals Ultra-Low Leakage Arithmetic Circuits Using Symmetric and Asymmetric FinFETs

2013 ◽  
Vol 2013 ◽  
pp. 1-13 ◽  
Author(s):  
Farid Moshgelani ◽  
Dhamin Al-Khalili ◽  
Côme Rozon
Keyword(s):  
Work Function ◽  
Leakage Current ◽  
Power Supply ◽  
Full Adder ◽  
Arithmetic Circuits ◽  
University Of Florida ◽  
Low Leakage ◽  
The University

We are examining different configurations and circuit topologies for arithmetic components such as adder and compressor circuits using both symmetric and asymmetric work-function FinFETs. Based on extensive characterization data, for the carry generation of a mirror full adder using symmetric devices, both leakage current and delay are decreased by 25% and 50%, respectively, compared to results in the literature. For the 14-transistor (14T) full adder topology, both leakage and delay are decreased by 23% and 29%, respectively, compared to the mirror topology. The 14T adder topology, using asymmetric devices without any additional power supply, achives reduction in leakage current by 85% with a small degradation of 7% in delay. The compressor circuits, using asymmetric devices for one of the proposed configurations, achieve reduction in both leakage current and delay by 86% and 4%, respectively. All simulations are based on a 25 nm FinFET technology using the University of Florida UFDG model.

Highly Reliable Metal Gate nMOSFETs by Improved CVD-WSix films with Work Function of 4.3eV

2004 ◽  
Vol 811 ◽  
Author(s):  
Kazuaki Nakajima ◽  
Hiroshi Nakazawa ◽  
Katsuyuki Sekine ◽  
Kouji Matsuo ◽  
Tomohiro Saito ◽  
...  
Keyword(s):  
Work Function ◽  
Leakage Current ◽  
Power Supply ◽  
Supply Voltage ◽  
Gate Length ◽  
Gate Electrode ◽  
Metal Gate ◽  
Power Supply Voltage ◽  
Drive Current

ABSTRACTIn this paper, we first propose an improved CVD-WSix metal gate suitable for use with nMOSFETs. Work function of CVD-WSi3.9 gate estimated from C-V measurements was 4.3eV. The nMOSFET using CVD-WSi3.9 gate electrode showed that Vth variation of L/W=1 μm/10μm nMOSFETs can be suppressed to be lower than 8mV in 22chip. In CVD-WSi3.9 gate MOSFETs with gate length of 50nm, a drive current of 636μA/μm was achieved for off-state leakage current of 35nA/μm at 1.0V of power supply voltage. By using CVD-WSi3.9 gate electrode, highly reliable metal gate nMOSFETs can be realized.

scholarly journals Detecting leakage current by infrared thermography method

2019 ◽  
Vol 16 (1) ◽  
pp. 200
Author(s):  
M Riduan B. M Shariff ◽  
M.F. L. Abdullah ◽  
M Yusop B. A Latiff ◽  
Ahmad B. Mohamad ◽  
Iszaizul B. Ismail
Keyword(s):  
Infrared Thermography ◽  
Leakage Current ◽  
Conventional Method ◽  
Power Supply ◽  
Radiation Power ◽  
Net Radiation ◽  
Current Leakage ◽  
Root Cause ◽  
Electrical Loads ◽  
Electrical Installation

<span>An alternating current leakage can happen in electrical installation such as switchgear panel. If it’s not being detected earlier and address properly, it might lead to unintended incident or accident such as fire, electric shock, and power supply trip. Occasionally, if it appears, tracing its root cause can be difficult. The conventional method is by isolating one by one of the electrical loads with aids of multimeter and clamp meter. <span class="apple-converted-space"> </span>Unfortunately, this conventional method could be a tedious job for installations involved in numbers of electrical panels. Therefore, an alternative method is deeming necessary. This paper describes research works on Infrared Thermography (IRT) as a new method in detecting leakage current as aids in resolving related electrical problems. The scope of study mingling around to determine IRT’s suitable parameters that represent the identification of leakage current, derive new mathematical equation correlating leakage current to IRT and conduct experiment accordingly. Two new equations derived which are leakage current relationship to thermogram and infrared net radiation power. The results of experiment adherence to the hypothesis drawn. Consequently, helps to realize predictive maintenance concept by detecting the root cause of leakage current ahead its triggering points of unintended incident and accident.</span>

The Design of Pressure Meter Based on Ultralow-Power Consumption Technique

2012 ◽  
Vol 605-607 ◽  
pp. 891-894
Author(s):  
Zhi Ying Xie ◽  
Li Ping Zheng ◽  
Han Zhang
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Power Supply ◽  
Hardware Design ◽  
Digital Pressure ◽  
Software And Hardware ◽  
Ultralow Power ◽  
Pressure Meter

Since our world is facing with the problem of short power supply, it would be helpful to control the power consumption with the supper low power-consuming digital pressure detector discussed in the paper. The detector is controlled with chip microcomputer MSP430, and its software and hardware design is given in this paper, and the inspection precision is proved to be 0.4 levels.

Study on PLC Interference Suppression Technique Monitoring System of the Airport Power Supply Equipment

2013 ◽  
Vol 325-326 ◽  
pp. 1206-1209
Author(s):  
Xiao Bin Wei ◽  
Yi Zhu ◽  
Song Lu ◽  
Wei Zhang
Keyword(s):  
Control System ◽  
Power Supply ◽  
Interference Suppression ◽  
Measurement And Control System ◽  
Suppression Technique ◽  
Supply Equipment ◽  
Software And Hardware ◽  
Electro Magnetic ◽  
And Control ◽  
Measurement And Control

In allusion to the airdrome Electro Magnetic Interference (EMI),researched and designed the software and hardware technique methods on interference suppression for Measurement and control system based on PLC of airdrome power supply equipment.

A HIGH-LEVEL TECHNIQUE FOR ESTIMATION AND OPTIMIZATION OF LEAKAGE POWER FOR FULL ADDER

2013 ◽  
Vol 12 (02) ◽  
pp. 1350011
Author(s):  
JAYRAM SHRIVAS ◽  
SHYAM AKASHE ◽  
NITESH TIWARI
Keyword(s):  
Leakage Current ◽  
Power Supply ◽  
Low Voltage ◽  
Full Adder ◽  
Leakage Power ◽  
Power Gating ◽  
Sleep Transistors ◽  
Power Application ◽  
High Level ◽  
Standby Mode

Optimization of power is a very important issue in low-voltage and low-power application. In this paper, we have proposed power gating technique to reduce leakage current and leakage power of one-bit full adder. In this power gating technique, we use two sleep transistors i.e., PMOS and NMOS. PMOS sleep transistor is inserted between power supply and pull up network. And NMOS sleep transistor is inserted between pull down network and ground terminal. These sleep transistors (PMOS and NMOS) are turned on when the circuit is working in active mode. And sleep transistors (PMOS and NMOS) are turned off when circuit is working in standby mode. We have simulated one-bit full adder and compared with the power gating technique using cadence virtuoso tool in 45 nm technology at 0.7 V at 27°C. By applying this technique, we have reduced leakage current from 2.935 pA to 1.905 pA and leakage power from 25.04μw to 9.233μw. By using this technique, we have reduced leakage power up to 63.12%.

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