The Design of Pressure Meter Based on Ultralow-Power Consumption Technique

2012 ◽  
Vol 605-607 ◽  
pp. 891-894
Author(s):  
Zhi Ying Xie ◽  
Li Ping Zheng ◽  
Han Zhang
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Power Supply ◽  
Hardware Design ◽  
Digital Pressure ◽  
Software And Hardware ◽  
Ultralow Power ◽  
Pressure Meter

Since our world is facing with the problem of short power supply, it would be helpful to control the power consumption with the supper low power-consuming digital pressure detector discussed in the paper. The detector is controlled with chip microcomputer MSP430, and its software and hardware design is given in this paper, and the inspection precision is proved to be 0.4 levels.

Rack Server Solution in Data Center

2015 ◽  
Author(s):  
Sheng Kang ◽  
Guofeng Chen ◽  
Chun Wang ◽  
Ruiquan Ding ◽  
Jiajun Zhang ◽  
...  
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Power Supply ◽  
Data Center ◽  
Power Efficiency ◽  
High Performance ◽  
High Efficiency ◽  
High Growth ◽  
General Purpose ◽  
Power Supplies

With the advent of big data and cloud computing solutions, enterprise demand for servers is increasing. There is especially high growth for Intel based x86 server platforms. Today’s datacenters are in constant pursuit of high performance/high availability computing solutions coupled with low power consumption and low heat generation and the ability to manage all of this through advanced telemetry data gathering. This paper showcases one such solution of an updated rack and server architecture that promises such improvements. The ability to manage server and data center power consumption and cooling more completely is critical in effectively managing datacenter costs and reducing the PUE in the data center. Traditional Intel based 1U and 2U form factor servers have existed in the data center for decades. These general purpose x86 server designs by the major OEM’s are, for all practical purposes, very similar in their power consumption and thermal output. Power supplies and thermal designs for server in the past have not been optimized for high efficiency. In addition, IT managers need to know more information about servers in order to optimize data center cooling and power use, an improved server/rack design needs to be built to take advantage of more efficient power supplies or PDU’s and more efficient means of cooling server compute resources than from traditional internal server fans. This is the constant pursuit of corporations looking at new ways to improving efficiency and gaining a competitive advantage. A new way to optimize power consumption and improve cooling is a complete redesign of the traditional server rack. Extracting internal server power supplies and server fans and centralizing these within the rack aims to achieve this goal. This type of design achieves an entirely new low power target by utilizing centralized, high efficiency PDU’s that power all servers within the rack. Cooling is improved by also utilizing large efficient rack based fans for airflow to all servers. Also, opening up the server design is to allow greater airflow across server components for improved cooling. This centralized power supply breaks through the traditional server power limits. Rack based PDU’s can adjust the power efficiency to a more optimum point. Combine this with the use of online + offline modes within one single power supply. Cold backup makes data center power to achieve optimal power efficiency. In addition, unifying the mechanical structure and thermal definitions within the rack solution for server cooling and PSU information allows IT to collect all server power and thermal information centrally for improved ease in analyzing and processing.

A LOW-POWER UWB TRANSCEIVER BY USE OF TRIGGER RECEIVING METHOD

2010 ◽  
Vol 19 (07) ◽  
pp. 1609-1619 ◽  
Author(s):  
SHENG ZHANG ◽  
ZHENG LI ◽  
MENGMENG LIU ◽  
XIAOKANG LIN
Keyword(s):  
Energy Consumption ◽  
Power Consumption ◽  
Low Power ◽  
Power Supply ◽  
Circuit Complexity ◽  
Cmos Process ◽  
Fully Integrated

This paper presents a novel non-coherent receiving algorithm termed trigger receiving algorithm. In comparison with conventional coherent receiving method, the trigger receiving algorithm needs neither local template nor correlation operation, thus both circuit complexity and power consumption are drastically reduced. Based on the proposed algorithm, a fully integrated transceiver was implemented in a 0.18 μ m CMOS process. It occupies an area of 0.44 mm2 and achieves a maximum chip rate of 40 Mbps with 7 mW energy consumption provided by a 1.8 V power supply.

A CLOCK GATED SUCCESSIVE APPROXIMATION REGISTER FOR A/D CONVERSIONS

2014 ◽  
Vol 23 (02) ◽  
pp. 1450023
Author(s):  
MOHAMED O. SHAKER ◽  
MAGDY A. BAYOUMI
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Successive Approximation ◽  
Power Supply ◽  
Cmos Technology ◽  
Clock Signal ◽  
Switching Activity ◽  
Successive Approximation Register ◽  
Simulation Results ◽  
Data Switching

A novel low power clock gated successive approximation register (SAR) is proposed. The new register is based on gating the clock signal when there is no data switching activity. It operates with fewer transistors and no redundant transitions which makes it suitable for low power applications. The proposed register consisting of 8 bits has been designed up to the layout level with 1 V power supply in 90 nm CMOS technology and has been simulated using SPECTRE. Simulation results have shown that the proposed register saves up to 75% of power consumption.

Development of New Type Centralized Engineering Seismograph

2013 ◽  
Vol 333-335 ◽  
pp. 2412-2416
Author(s):  
Jin Feng Yan ◽  
Ming Deng ◽  
Yan Jun Li ◽  
Qi Sheng Zhang
Keyword(s):  
Power Consumption ◽  
Embedded System ◽  
Low Power ◽  
Program Implementation ◽  
High Performance ◽  
Hardware Design ◽  
Low Power Consumption ◽  
System Solution ◽  
Software Program ◽  
New Type

SoPC technology is a high-performance, low-power consumption embedded system solution based on embedded microprocessor, providing a new way for developing new type centralized engineering seismograph. The paper presents the development of a new type centralized engineering seismograph based on SoPC technology, which adopts FPGA design based on SoPC technology for the hardware design and embedded software program development of the 48-channel engineering seismograph. According to actual needs of currently available centralized engineering seismograph, combining the actual characteristics of SoPC embedded technology, a portable, low-power consumption and high-performance new type centralized engineering seismograph is constructed. The paper describes the hardware design and software program implementation of the centralized engineering seismograph in detail.

scholarly journals A Hardware Approach of a Low-Power IoT Communication Interface by NXP FlexIO Module

2019 ◽  
Vol 25 (6) ◽  
pp. 35-39
Author(s):  
Libor Chrastecky ◽  
Jaromir Konecny ◽  
Martin Stankus ◽  
Michal Prauzek
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Total Power ◽  
Processing Unit ◽  
Embedded Devices ◽  
Communication Interface ◽  
Result Section ◽  
Central Processing ◽  
Total Power Consumption ◽  
Software And Hardware

This article describes implementation possibilities of specialized microcontroller peripherals, as hardware solution for Internet of Things (IoT) low-power communication, interfaces. In this contribution, authors use the NXP FlexIO periphery. Meanwhile, RFC1662 is used as a reference communication standard. Implementation of RFC1662 is performed by software and hardware approaches. The total power consumption is measured during experiments. In the result section, authors evaluate a time-consumption trade-off between the software approach running in Central Processing Unit (CPU) and hardware implementation using NXP FlexIO periphery. The results confirm that the hardware-based approach is effective in terms of power consumption. This method is applicable in IoT embedded devices.

scholarly journals Design of 16-Bit SAR ADC Using DTMOS Technique

2021 ◽  
Vol 12 (3) ◽  
pp. 3046-3054
Author(s):  
Yarlagadda Archana Et.al
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Power Supply ◽  
Sar Adc ◽  
Differential Amplifier ◽  
Common Mode ◽  
Biomedical Implant ◽  
Low Leakage ◽  
Noise Rejection ◽  
Proper Operation

This paper presents a 16-bit 100MS/s SAR ADC with 1V power supply for biomedical implant systems developed with low power technique i.e., DTMOS logic. It consists of a R-2R DAC, low-power comparator, a digital SAR logic with low-leakage. The designed comparator is a differential architecture that has used to have an excellent, common-mode noise rejection. Comparator was created for proper operation to remain in saturation and could be used with differential amplifier. The comparator is the chief block of power consumption, so we focused mainly much of ability we make to design this module. The ADC is designed using Cadence virtuoso with CMOS 45nm technology. For SFDR, SNR, ENOB and power consumption, the converter utilizes 63.97dB, 51.06 dB, 15.15 and 528.8uw.

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