Research and Design of Beamforming Device of SLC-LSCMA Algorithm Based on FPGA

2013 ◽  
Vol 347-350 ◽  
pp. 1677-1681
Author(s):  
Qing Fang Zhou ◽  
Yan Yan Yu ◽  
Lei Wang ◽  
Jun Yang
Keyword(s):  
Least Squares ◽  
Satellite Communications ◽  
Clock Frequency ◽  
Verilog Hdl ◽  
Description Language ◽  
Quartus Ii ◽  
Hardware Description ◽  
Timing Simulation ◽  
Array Beamforming ◽  
Research And Design

In this paper,we design a uniform circular array beamforming device of 16 yuan based on the least squares SLC-LSCMA algorithm (based on the linear subspace constrained least squares cma) high stability and rapid convergence for the foundation. The design of the complete beam-forming the SLC-LSCMA algorithm by plural, time-multiplier and accumulators, which uses less resources and faster than the traditional algorithm. The beamforming device uses hardware description language of Verilog HDL , and wires on the QUARTUS II 8.0. Finally the beamforming device is downloaded to the Alteras EP2C35F672C6, and its timing simulation can be run properly in the 50MHz clock frequency. This design can be widely used in mobile communication and satellite communications.

scholarly journals Study of Data Security Algorithms using Verilog HDL

2015 ◽  
Vol 5 (5) ◽  
pp. 1092
Author(s):  
M. Sumathi ◽  
D. Nirmala ◽  
R. Immanuel Rajkumar
Keyword(s):  
Performance Evaluation ◽  
Data Security ◽  
Hardware Description Language ◽  
Performance Study ◽  
Verilog Hdl ◽  
Description Language ◽  
Quartus Ii ◽  
Encryption And Decryption ◽  
Different Types ◽  
Hardware Description

This paper describes an overview of data security algorithms and its performance evaluation. AES, RC5 and SHA algorithms have been taken under this study. Three different types of security algorithms used to analyze the performance study. The designs were implemented in Quartus-II software. The results obtained for encryption and decryption procedures show a significant improvement on the performance of the three algorithms. In this paper, 128-bit AES, 64-bit of RC5 and 512-bit of SHA256 encryption and Decryption has been made using Verilog Hardware Description Language and simulated using ModelSim.

Implementation of CRC by Using FPGA in Data Communication

2013 ◽  
Vol 325-326 ◽  
pp. 1805-1808
Author(s):  
Lie Wang ◽  
Yi Jie Wang
Keyword(s):  
Hardware Implementation ◽  
Data Communication ◽  
Communication Process ◽  
Hardware Description Language ◽  
Verilog Hdl ◽  
Description Language ◽  
Communication Structure ◽  
Development Platform ◽  
Hardware Description ◽  
Analyze Data

By introducing the basic principle of ordinary CRC algorithm, the paper develops an algorithm which can be used to analyze data communication structure and construct design process. At the same time, it can be quickly implemented in the data communication process. The algorithm uses Verilog HDL hardware description language to complete all the design on ISE development platform. And it uses Xilinxs development board Virtex-II Pro to achieve the final realization. Compared with traditional methods, the algorithm is simple and intuitive, which reduces computational the delays and saves space. It also benefits hardware implementation.

A High Speed 8B/10B Encoder/Decoder Design Based on Low Cost FPGA

2012 ◽  
Vol 462 ◽  
pp. 361-367 ◽  
Author(s):  
Zhang Jin Chen ◽  
Guo Hai Zhong ◽  
Zhuo Bi
Keyword(s):  
High Speed ◽  
Single Channel ◽  
Low Cost ◽  
Maximum Frequency ◽  
Clock Frequency ◽  
Parallel Pipeline ◽  
Quartus Ii ◽  
Simulation Results ◽  
Decoder Design ◽  
Timing Simulation

A high speed 8B/10B Encoder/Decoder is presented in this paper. The Encoder/Decoder is based on Altera’s low cost FPGA Cyclone family. The Encoder/Decoder includes parallel pipeline structure. The Encoder/Decoder is applied to the Serializer/Deserializer (SERDES) of high-speed serial bus. The Encoder/Decoder is synthesized and simulated by Quartus II 9.1. The synthesis and analysis results show the maximum frequency is more than 359MHz. The timing simulation results show the clock frequency is more than 125 MHz. The single channel data rate of serial bus can get to 1.25Gbps. The proposed Encoder/Decoder can meet the requirements of most high-speed serial bus.

scholarly journals Design and Analysis of Radix-8/4/2 64b/32b Integer Divider Using COMPASS Cell Library

VLSI Design ◽  
2000 ◽  
Vol 11 (4) ◽  
pp. 331-338 ◽  
Author(s):  
Chua-Chin Wang ◽  
Chenn-Jung Huang ◽  
I-Yen Chang
Keyword(s):  
High Speed ◽  
Hardware Description Language ◽  
Verilog Hdl ◽  
Description Language ◽  
Throughput Rate ◽  
Cell Library ◽  
Conversion Algorithm ◽  
Hardware Description ◽  
Simulation Results

A high speed 64b/32b integer divider employing digit-recurrence division method and the on-the-fly conversion algorithm, wherein a fast normalizer is included, which is used as the pre-processor of the proposed integer divider. For the sake of enhancing throughput rate, the proposed divider uses a mixed radix-8/4/2 division instead of the traditional radix-2 division. On-the-fly remainder adjustment is also realized in the converter module of the divider. The entire design is written in Verilog HDL (hardware description language) employing COMPASS 0.6 μm 1P3M cell library (V3.0), and then synthesized by SYNOPSYS. The simulation results indicate that our design is a better option than the existing long divider designs.

Research and Design of Asynchronous FIFO Based on FPGA

2014 ◽  
Vol 644-650 ◽  
pp. 3440-3444
Author(s):  
Bing Qi Liu ◽  
Ming Zhe Liu ◽  
Gang Yang ◽  
Xiao Bo Mao ◽  
Huai Liang Li
Keyword(s):  
Design Method ◽  
Stable State ◽  
Gray Code ◽  
Validity And Reliability ◽  
Verilog Hdl ◽  
Simulation Test ◽  
Development Platform ◽  
Module Design ◽  
Quartus Ii ◽  
Research And Design

In this article, a design method of asynchronous FIFO memory based on FPGA is put forward. With FPGA as the core controller, We adopt Verilog HDL and top-down design method to build a top-level module design and also analyze the mark logic of asynchronous FIFO and the elimination of semi-stable state under Quartus II development platform. Besides, with the application of Gray code conversion technology, not only the reliable transmission of data is guaranteed but also design efficiency is improved. Through contrast experiment analysis and simulation test, the validity and reliability of asynchronous FIFO memory are verified, meeting the basic requirement that FIFO can hold more enough data without spillovers despite the fullness of data.

scholarly journals Modelling Gene-Protein-Reaction Associations on an FPGA

2019 ◽  
Author(s):  
Macauley Coggins
Keyword(s):  
Metabolic Model ◽  
Logic Device ◽  
Description Language ◽  
Metabolic Modelling ◽  
Quartus Ii ◽  
Hardware Description ◽  
Design Software ◽  
Genome Scale ◽  
The Relationship ◽  
Protein Reaction

Genome-Scale metabolic models have proven to be incredibly useful.Allowing researchers to model cellular functionality based upon gene expression. However as the number of genes and reactions increases it can become computationally demanding. The first step in genome-scale metabolic modelling is to model the relationship between genes and reactions in the form of Gene-Protein-Reaction Associations (GPRA). In this research we have developed a way to model GPRAs on an Altera Cyclone II FPGA using Quartus II programmable logic device design software and the VHDL hardware description language. The model consisting of 7 genes and 7 reactions was implemented using 7 combinational functions and 14 I/O pins. This model will be the first step towards creating a full genome scale metabolic model on FPGA devices which we will be fully investigating in future studies.

scholarly journals Hardware Implementation of Stockwell Transform and Smoothed Pseudo Wigner Ville Distribution Transform on FPGA using CORDIC Algorithm

2022 ◽  
Vol 10 (5) ◽  
pp. 57-60
Author(s):  
B Murali Krishna ◽  
◽  
B.T. Krishna ◽  
K Babulu ◽  
◽  
...  
Keyword(s):  
Cordic Algorithm ◽  
Matlab Simulation ◽  
Verilog Hdl ◽  
Description Language ◽  
S Transform ◽  
Field Programmable ◽  
Hardware Resource ◽  
Linear Transform ◽  
Hardware Description ◽  
Stockwell Transform

A comparison of linear and quadratic transform implementation on field programmable gate array (FPGA) is presented. Popular linear transform namely Stockwell Transform and Smoothed Pseudo Wigner Ville Distribution (SPWVD) transform from Quadratic transforms is considered for the implementation on FPGA. Both the transforms are coded in Verilog hardware description language (Verilog HDL). Complex calculations of transformation are performed by using CORDIC algorithm. From FPGA family, Spartan-6 is chosen as hardware device to implement. Synthetic chirp signal is taken as input to test the both designed transforms. Summary of hardware resource utilization on Spartan-6 for both the transforms is presented. Finally, it is observed that both the transforms S-Transform and SPWVD are computed with low elapsed time with respect to MATLAB simulation.

Mapping Based Energy Efficient Counter Design on FPGA

2014 ◽  
Vol 984-985 ◽  
pp. 1085-1088
Author(s):  
Tanesh Kumar ◽  
Bishwajeet Pandey ◽  
S.M. Mohaiminul Islam ◽  
Narpath Singh ◽  
S. Mahbubul Alam ◽  
...  
Keyword(s):  
Power Dissipation ◽  
Energy Efficient ◽  
Control Signal ◽  
Efficient Design ◽  
Verilog Hdl ◽  
Description Language ◽  
Design Synthesis ◽  
Hardware Description ◽  
Energy Efficient Design ◽  
Control Port

— In this work, 8-bit counter power optimized counter is designed with help of energy efficient techniques called mapping and simulation activity file in format of Value Change Dump (VCD) file and setting file (*.xpa) to define toggle rate, activity rate and enable rate for the power consumption estimation in order to get energy efficient design. With mapping, there is 33.33%, 34.61%, 36.5%, 36.49%, 36.86%, 36.9% dynamic power reduction in counter when device is operating on 10MHz, 100MHz, 1GHz, 10GHz, 100GHz and 1 THz frequency. This reduction achieved by mapping control signal to control port in place of mapping control signal to LUT (Look Up Table) input. In Resource utilization, when we are mapping the control signal to control port, there is 70.58% less number of LUT and 39.89% less number of IO usage than mapping the control signal to LUT inputs. Spartan-3 FPGA is taken as target device and Xilinx 14.1 ISE is taken as design, synthesis and implementation tools. Verilog HDL(Hardware Description Language) is used to synthesize the counter on FPGA. The power dissipation of the FPGA based energy efficient design is verified using Xilinx XPower tool.

The Design of the Multifunctional Electronic Timing System Based on the Verilog HDL Language

2012 ◽  
Vol 182-183 ◽  
pp. 763-767 ◽  
Author(s):  
Ming Zhang ◽  
Hao Ting Liu ◽  
Yu Wang
Keyword(s):  
Electronic Control ◽  
Verilog Hdl ◽  
Description Language ◽  
Hardware System ◽  
Timing System ◽  
Logic Verification ◽  
Timing Function ◽  
Hardware Description ◽  
Function Module ◽  
Clock Module

Verilog is the most widely used hardware description language. It can be used in the modeling, synthesis, and simulation stages of the hardware system designing. This thesis is about applying Verilog HDL to design the multifunctional electronic timing system. This system has brought about the timing function, the Alarm clock function, the time checking module, the stop clock module, the exact hour alarming module, the alarm clock’s shielding and alarming function module and the stop clock Prompting function module. The modules which have applied this design can be transplanted to other kinds of electronic control systems conveniently. This system uses the Verilog HDL to design, so it has nothing to do with the craft. It allows us to attain the applicable actual circuit easily without considering much about the details of the gate level and the realization of the craft in the function designing stage and the logic verification stage. We just need to exert different conditions according to the demand of the design of the system.

scholarly journals Modelling Gene-Protein-Reaction Associations on an FPGA

2019 ◽  
Author(s):  
Macauley Coggins
Keyword(s):  
Metabolic Model ◽  
Logic Device ◽  
Description Language ◽  
Metabolic Modelling ◽  
Quartus Ii ◽  
Hardware Description ◽  
Design Software ◽  
Genome Scale ◽  
The Relationship ◽  
Protein Reaction

AbstractGenome-Scale metabolic models have proven to be incredibly useful. Allowing researchers to model cellular functionality based upon gene expression. However as the number of genes and reactions increases it can become computationally demanding. The first step in genome-scale metabolic modelling is to model the relationship between genes and reactions in the form of Gene-Protein-Reaction Associations (GPRA). In this research we have developed a way to model GPRAs on an Altera Cyclone II FPGA using Quartus II programmable logic device design software and the VHDL hardware description language. The model consisting of 7 genes and 7 reactions was implemented using 7 combinational functions and 14 I/O pins. This model will be the first step towards creating a full genome scale metabolic model on FPGA devices which we will be fully investigating in future studies.

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