Ternary Logic Dynamic CMOS Comparators

2011 ◽  
Vol 317-319 ◽  
pp. 1177-1182 ◽  
Author(s):  
Xin Yu Jin ◽  
Cheng Li ◽  
Jun Biao Liu ◽  
Xiao Feng Jiang ◽  
Xiang Bing Zeng
Keyword(s):  
Power Consumption ◽  
Circuit Design ◽  
High Speed ◽  
Logic Circuit ◽  
New Method ◽  
Low Power Consumption ◽  
Memory Testing ◽  
Ternary Logic ◽  
Dynamic Cell ◽  
Self Test

In this paper, a new method of ternary logic circuit design is developed. It’s proposed that two types of static ternary CMOS comparators and three types of dynamic CMOS comparators, designed by new method, with low transistor count, high speed and low power consumption. The proposed comparators are the rearrangement and reordering of transistors in the evaluation block of a dynamic cell. These ternary comparators can be used as equality comparators, mutual comparators and zero/one/two detectors, which are widely used in build in self test and memory testing.

Design of Digital Operational Units with Low Power Consumption

2021 ◽  
Vol 12 (2) ◽  
pp. 63-73
Author(s):  
N. A. Avdeev ◽  
◽  
P. N. Bibilo ◽  
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
High Speed ◽  
Logic Circuits ◽  
Logic Circuit ◽  
Digital Design ◽  
Low Power Consumption ◽  
Structural Description ◽  
Clock Gating ◽  
Vhdl Code

The lowering of power consumption in CMOS VLSI digital systems is one of the most important problems that appear now for developers of CAD systems. One of the effective approaches to lowering the dynamic power consumption is creation of an algorithmic description of the VHDL project, which provides for the deactivation of some functional blocks which are not necessary in particular moments. Contemporary synthesizers fulfill the high level synthesis of logic circuits by substitution of description of each VHDL construction with functionally structural description of a proper logic subcircuit. The results of digital logic circuit synthesis (the number of logic elements and power consumption) depend significantly on initial VHDL code. During initial VHDL code development it is possible to use different approaches to improve some parameters of synthesized logic circuit. At the algorithmic level of the digital design, it is necessary to provide for disconnection of the units, which cause the higher power consumption. In this paper such methods of algorithmic VHDL description of logic circuit are studied. The efficiency of the proposed methods is compared with the traditional method of VHDL-description which does not take the aspect of power con­sumption into account and is oriented only to the correct functionality of the developed logic circuit. To estimate the power consumption of logic circuits the approach is used which allows applying high-speed logical VHDL-simulation of structural descriptions (netlists) of logic circuits instead of slow SPICE simulation. The main conclusion of the provided study is the following: the clock gating and the storage of operand values for complex operations as well as zero value setting for simple ones are effective methods for the VHDL description of operational units with low power consumption implemented in the CMOS basis.

scholarly journals Ultracompact and low-power-consumption silicon thermo-optic switch for high-speed data

Nanophotonics ◽  
2020 ◽  
Vol 10 (2) ◽  
pp. 937-945
Author(s):  
Ruihuan Zhang ◽  
Yu He ◽  
Yong Zhang ◽  
Shaohua An ◽  
Qingming Zhu ◽  
...  
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
High Speed ◽  
High Performance ◽  
Pulse Amplitude ◽  
Telecommunication Networks ◽  
Low Power Consumption ◽  
Power Efficient ◽  
High Speed Data ◽  
On Chip

AbstractUltracompact and low-power-consumption optical switches are desired for high-performance telecommunication networks and data centers. Here, we demonstrate an on-chip power-efficient 2 × 2 thermo-optic switch unit by using a suspended photonic crystal nanobeam structure. A submilliwatt switching power of 0.15 mW is obtained with a tuning efficiency of 7.71 nm/mW in a compact footprint of 60 μm × 16 μm. The bandwidth of the switch is properly designed for a four-level pulse amplitude modulation signal with a 124 Gb/s raw data rate. To the best of our knowledge, the proposed switch is the most power-efficient resonator-based thermo-optic switch unit with the highest tuning efficiency and data ever reported.

scholarly journals A high-speed hybrid Full Adder with low power consumption

2012 ◽  
Vol 9 (24) ◽  
pp. 1900-1905
Author(s):  
Kamran Delfan Hemmati ◽  
Mojtaba Behzad Fallahpour ◽  
Abbas Golmakani ◽  
Kamyar Delfan Hemmati
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
High Speed ◽  
Full Adder ◽  
Low Power Consumption

scholarly journals Integration of highly anisotropic multiferroic BaTiO3–Fe nanocomposite thin films on Si towards device applications

2020 ◽  
Vol 2 (9) ◽  
pp. 4172-4178
Author(s):  
Matias Kalaswad ◽  
Bruce Zhang ◽  
Xuejing Wang ◽  
Han Wang ◽  
Xingyao Gao ◽  
...  
Keyword(s):  
Thin Films ◽  
Power Consumption ◽  
Low Power ◽  
High Speed ◽  
Low Cost ◽  
Low Power Consumption ◽  
Silicon Substrates ◽  
Critical Step ◽  
Nanocomposite Thin Films ◽  
Device Applications

Integration of highly anisotropic multiferroic thin films on silicon substrates is a critical step towards low-cost devices, especially high-speed and low-power consumption memories.

Superlattice-like Ge 8 Sb 92 /Ge thin films for high speed and low power consumption phase change memory application

2014 ◽  
Vol 93 ◽  
pp. 4-7 ◽  
Author(s):  
Yifeng Hu ◽  
Xiaoyi Feng ◽  
Jiwei Zhai ◽  
Ting Wen ◽  
Tianshu Lai ◽  
...  
Keyword(s):  
Thin Films ◽  
Power Consumption ◽  
Low Power ◽  
Phase Change ◽  
High Speed ◽  
Phase Change Memory ◽  
Low Power Consumption ◽  
Change Memory
Sign in / Sign up

Export Citation Format

Share Document