Design of the Digital Phase Meter with GPIB Interface Based on FPGA
2012 ◽
Vol 490-495
◽
pp. 243-247
Keyword(s):
Comparing with the traditional phase meter, the design of digital phase meter with GPIB interface based on FPGA have some advantages, such as the high date transmission rate, the simple circuit, short design cycle and the lower price. The principle of this design meets with the standard of IEEE488.2 and use Verilog HDL language to design every interface. Then compile simulate it in Quartus II. Finally download it to the FPGA experiment board to realize every function. It makes the date transmission more stable and reliable through the design of GPIB interface
2014 ◽
Vol 644-650
◽
pp. 3440-3444
Keyword(s):
2019 ◽
Vol 892
◽
pp. 120-126
2015 ◽
Vol 738-739
◽
pp. 350-353
Keyword(s):
2013 ◽
Vol 347-350
◽
pp. 1677-1681
2020 ◽
Vol 617
◽
pp. 012026
2015 ◽
Vol 5
(5)
◽
pp. 1092
2013 ◽
Vol 380-384
◽
pp. 3312-3315
2013 ◽
Vol 380-384
◽
pp. 3643-3647
Keyword(s):