scholarly journals A New Technology for Reducing Power Consumption in Synchronous Digital Design Using Tri-State Buffer

2018 ◽  
Vol 11 (2) ◽  
pp. 60-66
Author(s):  
Hussein Shakor Moghee
Keyword(s):  
Power Consumption ◽  
Power Dissipation ◽  
New Technology ◽  
Reducing Power ◽  
Digital Design ◽  
Total Power ◽  
Verilog Hdl ◽  
Design And Implementation ◽  
Quartus Ii ◽  
State Technique

This research paper deals with design and implementation of low power 8-bit arithmetic logic units. The main part of power consumption is consumed in ALU in any processor. Therefore, reducing power dissipation in ALU should be requiring. The proposed technique disabled one of the main block of ALU using tri-state logic which is not necessary to use, except the required processes. In this work, the suggested design is realized by using ASIC methodologies. In order to implement the arithmetic and logic architectures, 130 nm standard cell libraries are used for ASIC execution. The architecture of the design has been created using Verilog HDL language. In addition, it is simulated using ModelSim-Altera 10.3c (Quartus II 14.1) tools. By using tri-state technique, dynamic power and total power are decreased

Power Consumption Saving of Chiller Water System for Semiconductor Factory in Taiwan

2011 ◽  
Vol 314-316 ◽  
pp. 1492-1501
Author(s):  
Ching Liang Chen ◽  
Yung Chung Chang
Keyword(s):  
Power Consumption ◽  
Water Supply ◽  
Water Temperature ◽  
Cooling Tower ◽  
Reducing Power ◽  
Total Power ◽  
Water Cooling ◽  
Cooling Temperature ◽  
Total Power Consumption ◽  
Temperature Water

Recently, the semiconductor manufacturing industry has exhibited not only fast growth, but intense power consumption. Consequently, reducing power consumption is critical for running reliability. A view of literature reveals that the power consumption of facility system is 56.6 % in the fabs. Among all facility systems, chiller plants are the largest energy users, consuming 27.2 % of the total power consumption. Therefore, saving power consumption for chiller plants involves a considerable economic benefit. In addition, cooling the water temperature further improves the efficiency of chillers. Hence, this report analyzes the optimal temperature between the chiller and cooling tower. Currently, controlling the chiller and cooling tower are separate processes, though, in fact, they should not be. This is because the water cooling temperature affects the efficiency of the chiller. Each reduced degree of the chiller condenser temperature reduces the electrical power by approximately 2 % in the cooling tower, in contrast to the chiller. Therefore, the optimal water cooling water temperature must be analyzed. The analysis method in this report is linear regression. First, determine the equations of power consumption for the chiller and cooling tower with variables representing the water cooling temperature, water supply temperature of the chiller, and outdoor loading and wet-bulb temperatures. Second, add the coefficient of the same variable to obtain the total power consumption equation for the chiller and cooling tower. The result shows the relationships of power consumption with water cooling temperature under identical conditions of the water cooling temperature, water supply temperature of chiller, and outdoor loading and wet-bulb temperatures. Finally, use the differential method to determine the optimal water cooling temperature.

scholarly journals Design of Low Power Transceiver on Spartan-3 and Spartan-6 FPGA

2019 ◽  
Vol 8 (12S2) ◽  
pp. 27-30
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Power Dissipation ◽  
Power Analysis ◽  
Research Work ◽  
Leakage Power ◽  
Total Power ◽  
Voltage Supply ◽  
Field Programmable ◽  
Eda Tools

In this research work, a low power transceiver is designed using Spartan-3 and Spartan-6 Field-Programmable Gate Array (FPGA). In this work, a Universal Asynchronous Receiver Transmitter (UART) device is used as a transceiver. The implementation of UART is possible with EDA tools called Xilinx 14.1 and the results of the power analysis are targeted on Spartan-3 and Spartan-6 FPGA. The variation of different power of chips that are fabricated on FPGA for e.g., Input/Output (I/O) power consumption, Leakage power dissipation, Signal power utilization, Logic power usage, and the use of Total power, is observed by changing the voltage supply. This research work shows how the change in voltage influence the power consumption of UART on Spartan-3 and Spartan-6 FPGA devices. It is observed that Spartan-6 is found to be more powerefficient as voltage supply increases.

Design and Implementation of Floyd-Steinberg Algorithm Based on FPGA

2015 ◽  
Vol 738-739 ◽  
pp. 350-353
Author(s):  
Jun Yang ◽  
Zong Jing Li ◽  
Wen Long Li
Keyword(s):  
Real Time ◽  
High Speed ◽  
Complex Multiplication ◽  
Error Diffusion ◽  
Computation Complexity ◽  
Time Error ◽  
Verilog Hdl ◽  
Memory Space ◽  
Design And Implementation ◽  
Quartus Ii

In this paper, we put forward an innovation method of high-speed and real-time error diffusion, which is based on Floyd-Steinberg algorithm. The design introduces LUT(look up table) and pipeline technology instead of complex multiplication operations, which accesses to the memory frequently. The whole design uses Verilog HDL language to program and Quartus ii 8.0 to synthesize and layout. At the end of the paper, we use a 48 pixel as an example, then simulate and verify it on the Modesim, which can prove the correctness of the design. Compared with the standard Floyed-Steinberg algorithm, this design can reduce the computation complexity, use a smaller memory space to exchange lots of logic units and increase the throughput of the algorithm. Besides, it has the advantages of good reconfigurability, simple hardware structure and high real-time.

scholarly journals A CLASS OF IRREDUNDANT ENCODING TECHNIQUES FOR REDUCING BUS POWER

2002 ◽  
Vol 11 (05) ◽  
pp. 445-457 ◽  
Author(s):  
YAZDAN AGHAGHIRI ◽  
FARZAN FALLAH ◽  
MASSOUD PEDRAM
Keyword(s):  
Power Consumption ◽  
Power Dissipation ◽  
Printed Circuit Board ◽  
Circuit Board ◽  
Total Power ◽  
Switching Activity ◽  
Printed Circuit ◽  
Memory Address ◽  
Total Power Consumption ◽  
Bus Encoding

This paper proposes a number of encoding techniques for decreasing power dissipation on global buses. The best target for these techniques is a wide and highly capacitive memory bus. Switching activity of the bus is reduced by means of encoding the values that are conveyed over them. More precisely, three irredundant bus-encoding techniques are presented in this paper. These techniques decrease the bus activity by as much as 86% for instruction addresses without the need to add redundant bus lines. Having no redundancy means that exercising these techniques on any existing system does not require redesign and remanufacturing of the printed circuit board of the system. The power dissipation of the encoder and decoder blocks is insignificant in comparison with the power saved on the memory address bus. This makes these techniques capable of reducing the total power consumption.

scholarly journals Performance Analysis of Dual Edge Triggered Memory Cells using Multiple C-Elements

2019 ◽  
Vol 8 (4) ◽  
pp. 8604-8607
Keyword(s):  
Energy Dissipation ◽  
Performance Analysis ◽  
Power Dissipation ◽  
Average Power ◽  
Reducing Power ◽  
Digital Design ◽  
Flip Flop ◽  
Static Power ◽  
Element Technique ◽  
Conditional Discharge

This research paper presents a low conditional discharge(C-element) Flip-Flops that are basic elements in all digital design. The existing circuits are power hunger due to the dynamic and static power dissipation increases. For reducing power consumption C element technique is used to reduce glitches at the data out. Results obtained through 130nm technology shows reduction in energy dissipation and delay. Average dynamic power dissipation of the proposed flip-flop is compare with two existing techniques. Average power of proposed flip-flop is reduced by 28.41% and 36.18% when compared with Latch-Mux flip-flop and Latch-Mux using Celement.

scholarly journals OS Level Power Optimization in LCMP

2019 ◽  
Vol 8 (4) ◽  
pp. 10089-10092
Keyword(s):  
Power Consumption ◽  
Power Dissipation ◽  
High Performance ◽  
Large Scale ◽  
Heat Dissipation ◽  
Power Optimization ◽  
Reducing Power ◽  
System Throughput ◽  
Thread Migration ◽  
Computing Power

With the increasing levels of transistor count and clock rate of microprocessors there is a significant increase in power dissipation. Reducing power consumption in both high power consumption and high performance has developed into one of the main target in designing a system for various devices. As the chip multiprocessor (CMP) are integrating more cores on the die, it will leads to the extent of Large scale CMP (LCMP) architectures with potentially hundreds of thread on the die and thousands of cores. Therefore, we proposed an approach of OS level power optimization in LCMP to optimize the heat dissipation rate and increase computing power under some considerations. To satisfy the main goal of our work, the heat dissipation should be optimizing with increase in computing power. The approach of optimizing the heat dissipation is done at the synthesis level. There are three approaches for modifying the synthetic benchmark: Singly Synthesis, Hierarchical Synthesis and Group Synthesis. The result is that the power dissipation of Group synthesis is equally distributed without giving more loads to only one processor as compared to Hierarchical Synthesis and Singly Synthesis. Therefore, from our result we can conclude that in Group Synthesis power is equally distributed hence heat dissipation is optimized. The future work will be to further optimize the result of the Synthesis level using thread migration. Thread Migration can increase the system throughput; it relies on multiple cores that vary in performance capabilities

Design and Implementation of Signal Generator Based on DDS

2013 ◽  
Vol 380-384 ◽  
pp. 3643-3647
Author(s):  
Hong He ◽  
Jin Zhou Zhang ◽  
Zhi Hong Zhang
Keyword(s):  
Duty Cycle ◽  
Pulse Width ◽  
Signal Generator ◽  
Direct Digital Synthesis ◽  
Verilog Hdl ◽  
Design And Implementation ◽  
Quartus Ii ◽  
Digital Synthesis ◽  
Frequency Phase

A signal generator with adjustable frequency, phase and duty cycle is designed in this paper. The design of this signal generator is based on the technology of direct digital synthesis (DDS).The classic structure of DDS is presented and its principles are introduced in detail. The key modules of the design such as phase accumulator and pulse width processing are implemented by verilog HDL language. With suitable FPGA, the designed signal generator and all modules of the design are simulated successfully in Quartus II.

scholarly journals Design and Implementation of Low-Cost Real-Time Energy Logger for Industrial and Home Applications

2021 ◽  
Author(s):  
Pooja R. Khanna ◽  
Gareth Howells ◽  
Pavlos I. Lazaridis
Keyword(s):  
Power Consumption ◽  
Real Time ◽  
Web Application ◽  
Single Phase ◽  
Total Power ◽  
Raspberry Pi ◽  
Energy Usage ◽  
Measurement Device ◽  
Design And Implementation ◽  
Total Power Consumption

AbstractWith the significant increase in energy demands in the last decade, the issues of unnecessary energy usage have increased rapidly. Therefore, there is an immediate need to provide a cheap and easily accessible monitoring tool for the energy consumed by an appliance used in homes and industries. Instead of monitoring the total power consumption of the houses and/or industries, it is useful to monitor the power consumption of the individual appliance, which in turn, helps in saving the overall energy usage and thereby makes it cost-effective. This paper presents a cost-efficient design and implementation of a monitoring system that can precisely measure the current and voltage of each appliance. The design provides tracking of device activity in a real-time environment for the industries and helps in adopting to the green initiative. The design comprises of Arduino based micro-controller and Raspberry Pi, that performs precise measurements of current and voltage of the device, followed by measuring the power consumed by the device. This paper presents two different system designs, one for the single-phase measurements and the other for the DC measurements. The single-phase measurement device comprises of 10-bit ADC whereas, the 24 V DC measurement device comprises of a 12-bit ADC, which provides higher measurement accuracy compared to other systems available in the market. The implemented design uses the EmonCMS web application to accumulate and envision the monitored data. It provides a flexible and user-friendly solution to monitor the measured data easily on any android or iOS devices.

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