Modeling and Simulation of Nanoscale Lateral Gaussian Doped Channel Asymmetric Double Gate MOSFET

2015 ◽  
Vol 36 ◽  
pp. 51-63 ◽  
Author(s):  
Vandana Kumari ◽  
Manoj Saxena ◽  
Mridula Gupta

This work presents the drain current model using Evanescent Mode Analysis (EMA) for nanoscale Double Gate MOSFET having Gaussian doping profile along the horizontal direction in the channel i.e. from source to drain region. Due to heavily doped channel, band gap narrowing effect is incorporated in the analytical modeling scheme. The various parameters evaluated in this work using analytical modeling scheme are surface potential, electric field, threshold voltage, sub-threshold slope and drain current. The impact of peak Gaussian doping profile on the drain current and trans-conductance has been demonstrated which are important for assessing the analog performance of the device. The results are also compared with the uniformly doped DG MOSFET. The asymmetric behaviour of Gaussian doped DG MOSFET has also been investigated. In addition to this, digital performance of Gaussian doped DG MOSFET has also been assessed using exhaustive device simulation.

2015 ◽  
Vol 36 ◽  
pp. 31-43
Author(s):  
Upasana ◽  
Rakhi Narang ◽  
Manoj Saxena ◽  
Mridula Gupta

The paper presents an in-depth study of device physics and development of a generalized model (Accumulation-Depletion-Inversion Mode) for Hetero-Dielectric based TFET Architecture. A comparative study among single dielectric (high-k and low-k dielectric materials) and dual-dielectric (Hetero-Dielectric) based p-i-n and p-n-i-n TFET architectures has also been made. The model includes the impact of dielectric length variation and mobile charge carriers which has been validated through the Vgs and Vds dependent effective potential at the channel center of the device. Several physics based parameters such as surface potential, energy band profile, total electric field and drain current (both Ids-Vds and Ids-Vds) have also been investigated. Further, the model has been extended to optimize the Hetero-Dielectric p-n-i-n TFET by tuning the gate work function and length of the dielectric material. While optimization various static parameters such as Subthreshold Swing (SS), threshold voltage, Ion/Ioff ratio and dynamic performance parameters (parasitic capacitances) i.e. total gate capacitance (Cgg), gate to source capacitance (Cgs) and gate to drain capacitance (Cgd) have been investigated. The efficacy of the model has been validated through simulation results obtained using ATLAS device simulator.


Author(s):  
Simone Leeuw ◽  
◽  
Viranjay M. Srivastava

The traditional buck regulator provides the steady output voltage with high efficiency and low power dissipation. Various parameters of this regulator can be improved by the placement of Double-Gate (DG) MOSFET. The double-gate MOSFET provides twice the drain current flow, which improves the various parameters of buck regulator structure and inevitably increases the device performance and efficiency. In this research work, these parameters have been analyzed with implemented DG MOSFET buck regulator and realized the total losses 42.676 mW and efficiency 74.208%. This research work has designed a DG MOSFET based buck regulator with the specification of input voltage 12 V, output voltage 3.3 V, maximum output current 40 mA, switching frequency 100 kHz, ripple current of 10%, and ripple voltage of 1%.


2011 ◽  
Vol 20 (9) ◽  
pp. 097304
Author(s):  
Xing-Ye Zhou ◽  
Jian Zhang ◽  
Zhi-Ze Zhou ◽  
Li-Ning Zhang ◽  
Chen-Yue Ma ◽  
...  

2012 ◽  
Vol 59 (10) ◽  
pp. 2567-2574 ◽  
Author(s):  
Vandana Kumari ◽  
Manoj Saxena ◽  
R. S. Gupta ◽  
Mridula Gupta

Sign in / Sign up

Export Citation Format

Share Document