AlON/SiO2 Stacked Gate Dielectrics for 4H-SiC MIS Devices

2009 ◽  
Vol 615-617 ◽  
pp. 541-544 ◽  
Author(s):  
Takuji Hosoi ◽  
Makoto Harada ◽  
Yusuke Kagei ◽  
Yuu Watanabe ◽  
Takayoshi Shimura ◽  
...  
Keyword(s):  
Gate Dielectric ◽  
Gate Dielectrics ◽  
Gate Insulator ◽  
Flat Band ◽  
Aluminum Oxynitride ◽  
Fixed Charges ◽  
Interface Charge ◽  
Capacitance Voltage ◽  
High Dielectric ◽  
Mis Devices

We propose the use of an aluminum oxynitride (AlON) gate insulator for 4H-SiC MIS devices. Since direct deposition of AlON on 4H-SiC substrate generates a large amount of interface charge due to an interfacial reaction, a thick AlON layer was deposited on underlying thin SiO2 thermally grown in N2O ambient. To reduce the negative fixed charge density in the aluminum oxide (Al2O3) film, we used reactive sputtering of Al in an N2/O2 gas mixture. The fabricated MIS capacitor with AlON/SiO2 stacked gate dielectric shows no flat band voltage shift and negligible capacitance-voltage hysteresis (30 mV), indicating the dielectric is almost free from both fixed charges and electrical defects. Owing to the high dielectric constant of AlON (k=6.9), as compared to single N2O-SiO2 gate insulator, significant gate leakage reduction was achieved by AlON/SiO2 stacked gate dielectrics even at high-temperature, especially in a high electric field condition (>5 MV/cm).

Radiation Hardness for Silicon Oxide and Aluminum Oxide on 4H-SiC

2018 ◽  
Vol 924 ◽  
pp. 229-232 ◽  
Author(s):  
Anders Hallén ◽  
Sethu Saveda Suvanam
Keyword(s):  
Proton Irradiation ◽  
Silicon Oxide ◽  
Positive Charge ◽  
Gate Dielectric ◽  
Radiation Hardness ◽  
Flat Band ◽  
Capacitance Voltage ◽  
Cv Measurements ◽  
Radiation Hard ◽  
Mos Structures

The radiation hardness of two dielectrics, SiO2and Al2O3, deposited on low doped, n-type 4H-SiC epitaxial layers has been investigated by exposing MOS structures involving these materials to MeV proton irradiation. The samples are examined by capacitance voltage (CV) measurements and, from the flat band voltage shift, it is concluded that positive charge is induced in the exposed structures detectable for fluence above 1×1011cm-2. The positive charge increases with proton fluence, but the SiO2/4H-SiC structures are slightly more sensitive, showing that Al2O3can provide a more radiation hard passivation, or gate dielectric for 4H-SiC devices.

NANOSTRUCTURAL PROPERTIES OF La2O3/HfO2 GATE DIELECTRICS

2012 ◽  
Vol 26 (14) ◽  
pp. 1250080 ◽  
Author(s):  
A. BAHARI ◽  
A. RAMZANNEJAD
Keyword(s):  
Gate Dielectric ◽  
Gate Dielectrics ◽  
Wide Band ◽  
Amorphous Structure ◽  
Boron Diffusion ◽  
Wide Band Gap ◽  
Good Thermal Stability ◽  
Force Microscopy ◽  
Alternative Material ◽  
High Dielectric

There are some issues such as tunneling, leakage currents and boron diffusion through the ultra thin SiO 2 which are threatening ultra thin SiO 2 dielectric as a good gate dielectric. A very obvious alternative material is HfO 2, due to its high dielectric constant, wide band gap and good thermal stability on silicon substrate. We have thus demonstrated a number of processes to synthesize La 2 O 3/ HfO 2 and studied its nano structural properties with using X-ray diffraction (XRD), Fourier transform infrared spectroscopy (FTIR), scanning electron microscopy (SEM) and atomic force microscopy (AFM) techniques. The obtained results show that La 2 O 3/ HfO 2 (at 500°C with amorphous structure) can be introduced as a good gate dielectric for the future of complementary metal insulator semiconductor (CMIS) device.

Hrtem Investigation of Effect of Various Rare Earth Oxide Dopants on Epitaxial Zirconia High-k Gate Dielectrics

2002 ◽  
Vol 747 ◽  
Author(s):  
Takanori Kiguchi ◽  
Naoki Wakiya ◽  
Kazuo Shinozaki ◽  
Nobuyasu Mzutani
Keyword(s):  
Rare Earth ◽  
Ionic Radius ◽  
Gate Dielectric ◽  
Gate Dielectrics ◽  
Rare Earth Oxide ◽  
The Other ◽  
High K ◽  
Capacitance Voltage

ABSTRACTThe effects of several rare earth oxide on the capacitance-voltage (C-V) characteristics and the SiO2 interlayer growth of ZrO2 based gate dielectrics were examined. The width of the hysteresis window of La2O3 stabilized ZrO2 (LaSZ) gate dielectric was only 0.2V, on the other hands, that of Sc2O3 stabilized ZrO2 (ScSZ) gate dielectric was 1.4V HRTEM analysis indicated that the growth of SiO2 interlayer of RSZ (R=Sm,Nd,La) gate dielectric was about 1nm, which was less than half of the ScSZ one. These results indicate the advantage of the ZrO2 gate dielectric doped with rare earth oxide composed of larger ionic radius cation.

Hrtem Investigation of Effect of Various Rare Earth Oxide Dopants on Epitaxial Zirconia High-K Gate Dielectrics

2002 ◽  
Vol 745 ◽  
Author(s):  
Takanori Kiguchi ◽  
Naoki Wakiya ◽  
Kazuo Shinozaki ◽  
Nobuyasu Mzutani
Keyword(s):  
Rare Earth ◽  
Ionic Radius ◽  
Gate Dielectric ◽  
Gate Dielectrics ◽  
Rare Earth Oxide ◽  
The Other ◽  
High K ◽  
Capacitance Voltage

ABSTRACTThe effects of several rare earth oxide on the capacitance-voltage (C-V) characteristics and the SiO2 interlayer growth of ZrO2 based gate dielectrics were examined. The width of the hysteresis window of La2O3 stabilized ZrO2 (LaSZ) gate dielectric was only 0.2V, on the other hands, that of Sc2O3 stabilized ZrO2 (ScSZ) gate dielectric was 1.4V HRTEM analysis indicated that the growth of SiO2 interlayer of RSZ (R=Sm,Nd,La) gate dielectric was about 1nm, which was less than half of the ScSZ one. These results indicate the advantage of the ZrO2 gate dielectric doped with rare earth oxide composed of larger ionic radius cation.

Characterization of the Seed SiO2 Layer in Stacked SiO2-Ta2O5 Gate Dielectrics

1999 ◽  
Vol 567 ◽  
Author(s):  
Pradip K. Roy ◽  
Michael A. Laughery ◽  
Carlos M. Chacon ◽  
Ayman M. Kanan ◽  
Thomas Daugherty
Keyword(s):  
Gate Dielectric ◽  
Gate Dielectrics ◽  
Chemical Vapor ◽  
Charge Trapping ◽  
Oxide Semiconductor ◽  
Organic Chemical ◽  
Trap States ◽  
Electrical Measurements ◽  
High Concentrations ◽  
High Dielectric

ABSTRACTA major hurdle in the gate dielectric scaling using conventionally grown SiO2 has been excessive tunneling that occurs in ultra-thin (<25Å) SiO2. High dielectric constant materials have high concentrations of bulk fixed charge, unacceptable levels of Si-Ta2O5 interface trap states, and low Silicon interface carrier mobilities. Stacked Ta2O5 gate dielectrics have alleviated these issues with significant improvements in leakage, tunneling, charge trapping behavior, and interface substructure. Transistors fabricated using this stacked gate dielectric exhibit excellent sub threshold, saturation, and drive currents. In this study, we have characterized the first SiO2 (8-12Å) layer of the SiO2-Ta2O5 stack by ThermaWave (TWI 5240SE) absolute ellipsometry (AE) using He-Ne (λ= 630nm) laser light source and by corona oxide semiconductor (COS) non-contact techniques. We have also monitored the kinetics of a thin hydrocarbon layer deposition on top of these films that can be removed by simple heat treatments (250°C - 400°C). Electrical thickness (Tox) of these oxides measured by COS indicates this hydrocarbon layer has no impact on Tox. Stacked Ta2O5 was synthesized by metal organic chemical vapor deposition (MOCVD) of a 50-75Å thick Ta2O5 layer at 480°C, 300mTorr followed by an in-situ 550°C UV-03 anneal to densify the Ta2O5 film and grow an additional 5Å SiO2 layer underneath the first grown SiO2 layer resulting in an effective SiO2 thickness of 25-30Å (process 1). We have done exactly the same deposition schedule after chemically removing the first LP grown SiO2 layer resulting in an effective SiO2 thickness of 15-20Å (process 2). Transistors are now fabricated for our sub-0.16μm CMOS technologies. These stacked films indicated excellent charge trapping (Dit, Vfb, Qtot), leakage and tunneling characteristics from COS electrical measurements.

scholarly journals Analysis of Interface Charge Using Capacitance-Voltage Method for Ultra Thin HfO2 Gate Dielectric Based MOS Devices

2015 ◽  
Vol 57 ◽  
pp. 757-760 ◽  
Author(s):  
N.P. Maity ◽  
R.R. Thakur ◽  
Reshmi Maity ◽  
R.K. Thapa ◽  
S. Baishya
Keyword(s):  
Gate Dielectric ◽  
Mos Devices ◽  
Interface Charge ◽  
Capacitance Voltage

Effect of interface traps for ultra-thin high-k gate dielectric based MIS devices on the capacitance-voltage characteristics

2017 ◽  
Vol 75 ◽  
pp. 154-161 ◽  
Author(s):  
Slah Hlali ◽  
Neila Hizem ◽  
Liviu Militaru ◽  
Adel Kalboussi ◽  
Abdelkader Souifi
Keyword(s):  
Gate Dielectric ◽  
Interface Traps ◽  
High K ◽  
Capacitance Voltage ◽  
Mis Devices ◽  
High K Gate Dielectric

Study of SrTiO3 Gate Dielectrics

2006 ◽  
Vol 966 ◽  
Author(s):  
C.Y. Liu ◽  
Tseung-Yuen Tseng
Keyword(s):  
Dielectric Constant ◽  
Electrical Properties ◽  
Silicon Substrate ◽  
Interfacial Layer ◽  
High Dielectric Constant ◽  
Gate Dielectric ◽  
Gate Dielectrics ◽  
Measurement Techniques ◽  
High Quality ◽  
High Dielectric

ABSTRACTAmong various possible candidates of high-k gate dielectrics, SrTiO3 plays an important role because it has high dielectric constant and it can be epitaxially grown on silicon substrate. The fabrication process and properties of SrTiO3 gate dielectrics are reported. The effect of the addition of SiO2 on the microstructure and electrical properties of SrTiO3 gate dielectric is also presented. The minimization of the effect of interfacial layer between SrTiO3 and Si is the most important issue for obtaining high quality high-k gate dielectrics. The possible methods to improve the interfacial properties and the measurement techniques to characterize the interfacial layer are discussed.

Insulator/GaN Heterostructures of Low Interfacial Density of States

2000 ◽  
Vol 622 ◽  
Author(s):  
M. Hong ◽  
H. M. Ng ◽  
J. Kwo ◽  
A. R. Kortan ◽  
J. N. Baillargeon ◽  
...  
Keyword(s):  
Density Of States ◽  
Recent Progress ◽  
Gate Dielectric ◽  
Gate Dielectrics ◽  
Metal Insulator ◽  
Capacitance Voltage

ABSTRACTA review is given on insulators (oxides and nitrides) which have been deposited on GaN to form metal-insulator (oxides and nitrides)-semiconductor (MOS or MIS) diodes with a low interfacial density of states (Dit). These insulators include AlN, SiO2, Si3N4, SiO2/Ga2O3, and Ga2O3(Gd2O3). Techniques for depositing these insulators and methods for cleaning GaN surfaces prior to the insulator deposition are discussed. Recent progress on GaN MOSFET's (with SiO2/Ga2O3, and Ga2O3(Gd2O3) as gate dielectrics) and MISFET's (with AlN as a gate dielectric) is also reviewed. When exposed to room air, GaN surface is not as robust as previously thought. Therefore, preparation of a clean GaN surface for deposition of oxides and nitrides is necessary to achieve a low Dit. By heating GaN samples in UHV to clean the surfaces followed by deposition of Ga2O3(Gd2O3) and SiO2, we have achieved a low Dit with negligible hysteretic loops in the capacitance-voltage curves

Effect of Post-Metallization Hydrogen Annealing on C-V Characteristic of Zirconia Grown Using Atomic Layer Deposition

2002 ◽  
Vol 745 ◽  
Author(s):  
Arpan Chakraborty ◽  
Anil U. Mane ◽  
S. A. Shivashankar ◽  
V. Venkataraman
Keyword(s):  
Gate Dielectric ◽  
Gate Dielectrics ◽  
Charge Trapping ◽  
Atomic Layer ◽  
Flat Band ◽  
Hydrogen Annealing ◽  
Mos Capacitors ◽  
Hysteresis Width ◽  
Layer Deposition ◽  
Different Temperatures

ABSTRACTSubstantial amount of fixed charge present in most of the alternative gate dielectrics gives rise to large shifts in the flat-band voltage (VFB) and charge trapping and de-trapping causes hysterectic changes on voltage cycling. Both phenomena affect stable and reliable transistor operation. In this paper we have studied for the first time the effect of post-metallization hydrogen annealing on the C-V curve of MOS capacitors employing zirconia, one of the most promising gate dielectric. Samples were annealed in hydrogen ambient for up to 30 minutes at different temperatures ranging from room temperature to 400°C. C-V measurements were done after annealing at each temperature and the hysteresis width was calculated from the C-V curves. A minimum hysteresis width of ∼35 mV was observed on annealing the sample at 200°C confirming the excellent suitability of this dielectric.

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